Abstract: In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM memory cell. The access speed of the DRAM is dependent on the speed of the transition, due to this amplification, of the bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels. The transition speed of the bitline pairs can be increased by providing a higher overdrive voltage to the sense amplifier. As DRAM technologies are scaled successively smaller, the overdrive voltage must be controlled to avoid compromising the reliability of the DRAM. Accordingly, the present invention relates to a DRAM circuit which provides a transiently higher overdrive voltage only during sensing. The overdrive is provided by a pre-charged capacitive source utilizing the circuit's natural capacitance.