Abstract: A DRAM is formed using a process which uses few critical lithography steps and which provides capacitor electrodes and bit line contacts in a self-aligned manner in a common set of processing steps. A multilayer stack including a gate oxide layer, a gate electrode layer, an etch stop layer, and a thicker sacrificial layer are provided over the active device regions of a semiconductor substrate. Photolithography and etching define gate electrodes and wiring lines with patterned etch stop layers and patterned sacrificial layers over and self-aligned with the gate electrodes and wiring lines. Source/drain regions are formed self aligned to the patterned stacks and then an insulating spacer is provided alongside the edges of the gate electrodes. A relatively thin, conformal polysilicon layer is provided over the patterned stacks and in contact with the source/drain regions adjacent the gate electrodes.

Abstract: An adjustable method for making trenches for a semiconductor IC device having eliminated top corners is disclosed. The adjustable method includes forming a masking layer on the surface of the silicon nitride layer covering the device substrate that has openings corresponding to the openings of the trenches formed. Dimension of the masking layer opening is relatively greater than the dimension of the opening of the corresponding trench. An anisotropic etching procedure is then performed against the portions of the device substrate exposed out of the coverage of the masking layer, and the anisotropic etching shapes the trench sidewalls into sloped ones having larger dimension at the opening than at the surface of the filling material inside the trenches. This eliminates the top corners at the edges of the trench opening, charge accumulation and consequent leakage current can thus be prevented.