Abstract: Methods and apparatus for the processing of digital signals having high speed and low power dissipation. The apparatus uses Residue Number Systems (RNSs) to represent the signals and/or parameters, with each digit within an RNS system being encoded in a "one-hot" encoding scheme wherein each possible value of a digit has an associated single line, one and only one of which will be high at any one time. The combination of an RNS system with the one-hot scheme results in low signal activity and low loading of signal lines which in turn result in low power. Methods and apparatus for addition, subtraction, multiplication and other operations, and conversion from and to natural numbers. The speed advantage offered by other RNS-based architectures is retained.
Abstract: A method and apparatus for determining representative values for the chrominance components to be associated with a plurality of luminance components in a horizontally shrunken or stretched image for graphics controllers wherein display image data is stored in a buffer memory in a form associating a single set of U and V chrominance components with a plurality of Y luminance values. For a four to one shrinkage of an image in a format associating one set of chrominance components with four pixel luminance values wherein each pixel luminance value in the shrunken image initially has as associated set of chrominance components U.sub.0, U.sub.1, U.sub.2 and U.sub.3 and V.sub.0, V.sub.1, V.sub.2 and V.sub.3, the multiple values of the chrominance components are sequentially accumulated in a 3/4:1/4 ratio in such a manner as to provide an approximate average value for U and V for each set of four pixel luminance values in the shrunken image.
Type:
Grant
Filed:
March 2, 1998
Date of Patent:
July 27, 1999
Assignee:
Cirrus Logic, Inc.
Inventors:
Vernon Dennis Hasz, Karl Scott Mills, Richard Charles Andrew Owen, Mark Emil Bonnelycke
Abstract: An apparatus and method of generating redundancy symbols and syndromes which is order-programmable is disclosed. The apparatus and method involves the implementation of an error correcting encoder/decoder for polynomial codes which uses a single circuit to generate check symbols during the transmit operation and to generate syndromes during a receive operation. The selection of roots for the code generator, and hence, the code order is programmable.
Abstract: A transaction queue for transferring data between a host bus and an internal system bus within a graphics controller is disclosed. The queue comprises a First In First Out (FIFO) memory having independent clocks for reading and writing. The queue accommodates address information, data, command information, byte enable information, decode information, and a tag. The tag is a 2 bit field used to identify the queued entries as address, last data, and burst data. In a preferred embodiment, single transactions are written to the queue with no wait states. In the case of an address entry, the address associated with the transaction is stored in the queue along with the command and decode information. A tag is also included that identifies the entry as an address. In the case of a final data entry, the data is stored in the next entry along with the byte enable information and a tag to indicate it is the last data of the transaction.
Type:
Grant
Filed:
September 29, 1995
Date of Patent:
May 5, 1998
Assignee:
Cirrus Logic, Inc.
Inventors:
Karl Scott Mills, Lauren Emory Linstad, Sherwood Brannon, Mark Emil Bonnelycke, Richard Charles Andrew Owen
Abstract: A high voltage pulse power generating circuit capable of providing energy recovery is disclosed. The energy efficient pulse generating circuit source comprises a high voltage charge storing element which is periodically discharged into a compressor circuit. An energy recovery circuit coupled to the compressor circuit reverses the polarity of energy dissipated by the pulse power generating circuit and transfers the waste energy back to the power source. In a preferred embodiment, the pulse power generating circuit of the present invention utilizes an SCR switch for periodically discharging the charge storing element. This embodiment of the present invention provides pulses consistently and will not provide even a single missed pulse.
Type:
Grant
Filed:
October 31, 1996
Date of Patent:
March 17, 1998
Assignees:
Cymer, Inc., Advanced Pulse Power Technologies, Inc.
Inventors:
Daniel L. Birx, Palash P. Das, Igor V. Fomenkov, William N. Partlo, Tom A. Watson
Abstract: An apparatus and method of replacing the Master Boot Record with an installation code which retains compatibility with any disk partitioning or formatting utility that uses the system's BIOS to access the disk is disclosed. The Master Boot Record which is generally located on cylinder 0, head 0, sector 1 on a disk drive is replaced with a new BIOS loader and BIOS extension code. The BIOS loader determines the location in memory to load the new BIOS and updates the interrupt table. Upon completion of initialization, the new BIOS returns control to the BIOS Boot loader which requests the BIOS to load sector 1, head 0, track 0 to memory and then transfers control to it. The newly loaded BIOS extension redirects the request for this particular sector from 0/0/1 to the highest commonly available sector for cylinder 0 and track 0. Thereafter, all utilities which require access to the Master Boot Record will be transparently re-directed.
Abstract: A general-purpose, single-pass, adaptive, and lossless data compression invention implements an LZ1-like method using a hash-based architecture. It is suitable for use in data storage and data communications applications. Implementation efficiency, in terms of required memory and logic gates relative to the typical compression ratio achieved, is highly optimized. An easy-to-implement and quick-to-verify hash function is used. Differential copy lengths may be used to reduce the number of bits required to encode the copy-length field within copy tokens. That is, if multiple matches to a sequence of input bytes are found in the current window, then the length of the copy may be encoded as the difference between the lengths of the longest and the second-longest match, which results in a smaller copy length which likely has a shorter encoded representation.
Abstract: Forward link communication is achieved utilizing a conventional television broadcast station, either utilizing an entire presently unused TV channel or in a shared TV mode, with the return link communication being achieved using narrow band communication techniques for relatively low data rate communication through conventional television receiver aerials to a central receiver near the television station transmitter. The carrier reference of a local AM radio station is used as a synchronizing reference for the data streams and to allow the very close sepraration of each band in the return communication link to allow a large number of remote receivers to simultaneously communicate in the reverse link. Alternatively, the TV Chroma subcarrier serves this purpose.