Abstract: A digital cellular time-division multiple access (TDMA) system including a cellular switch and at least one base site employing 6:1 packing of transcoded information. The system incorporates the VSELP speech encoding algorithm to transcode data input from a cellular switch and a unique packing scheme to compress six messages channels worth of transcoded data into one 20 msec, 160 frame information block for transmission in one TDM timeslot. The compressed transcoded data is transmitted to a base-site on a T1 link where the six message channels worth of transcoded data is un-packed and coded. The coded information is then separated into two groups of three air-interface timeslots where two separate transmitters transmit one group each of three air-interface timeslots on two separate radio carrier frequencies.

Abstract: A single-block ceramic filter (102) is coupled to two antennas (142 and 144) for providing both antenna duplexing and antenna-summed diversity in a duplex radio transceiver (100). One antenna (142) is coupled by the filter (102) to a transmitter (132) and to a receiver (130), and a second antenna (144) is switchably coupled by the filter (102) to the receiver (130) by diversity control circuitry (101) in response to a diversity control signal (137). A microcomputer (134) in the transceiver (100) is coupled to the receiver (130) for monitoring the received signal strength (135). When the received signal strength (135) drops in level indicating that the signal being received on the antennas (142 to 144) has become degraded due to fading or other interference, the microcomputer (134) changes the binary state of the diversity control signal (137) for switching the receiver (130) between antenna (142) and both antennas (142 and 144).

Abstract: A unique cellular telephone controller (104 and 106) provides synthesized voice feedback for directory number confirmation, call status, and cellular telephone feature, option and service selection. Cellular telephone (100) includes a cellular telephone transceiver (102), cellular telephone handset (108), AM/FM radio (110), speaker (112), control box (106), and controller switch unit (104). Controller switch unit (104) includes phone switch (201), select switch (202), scroll up switch (203), scroll down switch (204), microphone (210), and preamplifier (211). Activation of the scroll up switch (203) or scroll down switch (204) steps a location counter through locations zero through ten of the telephone number directory in cellular telephone (100) and also voices the location number or name. Activation of the select switch (202) reads out the telephone number from the memory location indicated by the location counter and also voices the digits or name for the read-out telephone number.

Abstract: A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).

Abstract: A double annular ring gasket (202) interfaces a speaker (201) to a housing (200) in a portable radiotelephone, providing a conformal and acoustic seal between the speaker (201) and the housing (200), and compensating for dimensional tolerance between the housing (200) and the circuit board subassembly (204) on which the speaker (201) is mounted. The gasket (201) includes outer ring (205), inner ring (206) and intermediate ring (207) therebetween. The gasket (202) is inserted into a cavity (203) in the housing (200). Then, the speaker (201), as part of a printed circuit board subassembly (204), is pressed into place against the outer ring (205) of gasket (202) to form an axial seal and the inner ring (206) is deformed radially by the speaker (201) to form a conformal seal.

Abstract: A multiple latched accumulator fractional-N synthesizer for use in digital radio transceivers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615, 617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The carry outputs of each accumulator are coupled through delays (645, 647, 649, 631, 633) equal to one less delay than the number of accumulators and added (635) such that all higher order accumulator carry outputs add to a net summation of zero so as to not upset the desired fractional setting of the first accumulator.

Abstract: A fractional-division synthesizer for a digital transceiver is disclosed in which the fractional divisor may be separated into an integer, N, and a fraction made up of two integers, [n/d]. The integer n is the numerator of the fraction part of the fractional divisor. The integer N is the whole number portion of the fractional divisor. The integer d multiplied by the value of the transceiver channel spacing is algebraically related to the frequency of the reference oscillator. A bit rate clock is also derived from the reference oscillator.

Abstract: A PCM telephone switch that is simultaneously compatible with both DS-1 and CEPT PCM formats is disclosed. A switch module performs timeslot switching of individual subchannels between DS-1 and CEPT trunks which are input by way of digital group interfaces. Each group interface couples to one or more trunks of serial bit streams of either DS-1 or CEPT format standards. After the input serial bit stream is converted to a parallel format, it is used as eight bits of the address bits of data processing ROMs from which a corresponding 8-bit word is parallel read on a per channel basis and routed to the appropriate output data processing ROMs. The output data bits of the ROMs are the processed data bits which are reconverted to serial format for either DS-1 or CEPT standards as required by the output trunk. A-law or .mu.-law decoding and encoding is accomplished independently from input to output channel on a per channel basis.

Abstract: A battery charger having positioning and support apparatus for aligning batteries of varying sizes is disclosed. A recess in the battery charger housing has tapering sides which produce a charging pocket wider toward the front of the charger than toward the rear. Batteries of varying thickness have sloping sides which conform to the angle of taper of the battery charger. Rib members on the tapering sides engage slots in the batteries such that the batteries upon insertion into the charging pocket are initially guided by the tapering sides and then accurately positioned by the rib members.

Abstract: A controller for a radiotelephone having the capability of operation in both a secure mode for call authorization and a nonsecure mode for user interface is disclosed. The nonsecure mode and secure mode of operation are both resident in a single microcontroller which runs the nonsecure operations until a requirement for the secure operation is requested during call placement. The nonsecure mode is disabled during the period of time the secure mode is operational and is reenabled upon completion of the secure mode operation. The secure mode cannot be accessed externally to the microcontroller.

Abstract: A frequency synthesizer having a frequency divider and a frequency multiplier in the feedback loop is disclosed. The minimum frequency separation between two adjacent synthesized channels is equal to the reference frequency divided by the multiplication ratio of the multiplier. The division ratio of the frequency divider, which can be analyzed as the sum of an integer and a fractional portion, is varied with time by a digital sequence, resulting in a minimum frequency increment equal to a fraction of the reference frequency. The multiplier acts to reduce the nonlinearities of the frequency synthesizer when the fractional portion of the division ratio causes a large variation in the instantaneous division ratio by reducing the effective division ratio of the loop.

Abstract: In a PLL synthesizer, the tolerance to gain and component variations is greatly reduced when the gain of the loop in increased above that which the loop was initially designed for and if the third order loop symmetric ratio is reduced to a value within the range of 2.0 to 2.5. Higher order loops based on the third order symmetric ratio range have correspondingly lower transmission pole frequency to open unity gain frequency ratios.

Abstract: A fractional-N synthesizer employing at least a second order sigma-delta modulator is disclosed. The most significant bits from the output accumulator of the sigma-delta modulator are used as the carry out control for the variable divisor of the loop divider. Modulation to the synthesizer is introduced as part of the digital number input to the sigma-delta modulator and spurious signal output is reduced by selection of a large number as the denominator of the fractional portion of the loop divider divisor.