Abstract: A flight critical computer system for an aircraft includes dual independent lanes having two processors in each lane. The first lane has a primary processor and a redundant processor and provides a first command signal. The second lane includes a primary processor and a redundant processor and provides a second command signal. A first monitor compares the primary processor of the first lane with the primary processor of the second lane and generates first comparison signals as a function of disagreement therebetween. A second monitor compares the output signals of the redundant processor of the second lane and the primary processor of the first lane and generates second comparison signals as a function of disagreement therebetween. A third monitor compares the primary processor of the second lane with the redundant processor of the first lane and generates third comparison signals as a function of disagreement therebetween.