Patents Represented by Attorney Ron Feece
  • Patent number: 6392566
    Abstract: A method and apparatus are provided for modulating code for use with written optical disks such as digital video disks (DVD). The invention falitates 8/16 modulation by eliminating duplicate code conversion and by reducing the number of times that conversion codes must be looked up from a conversion table. A conversion code corresponding to a received input code is specified from among a plurality of conversion codes. Duplication information corresponding to the input code is read from a pre-processing table and duplicate information indicated duplicate conversion codes in the plurality of conversion codes is stored. Conversion code corresponding to the input code is read from the conversion table and is selectively stored with duplicate conversion codes being omitted.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: May 21, 2002
    Assignee: International Business Machines Corporation
    Inventor: Teruhiko Ushio
  • Patent number: 6370098
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: April 9, 2002
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Patent number: 6357030
    Abstract: A method and apparatus for efficiently encoding an ECC block for improving writing performance of a storage device using an ECC block format having a linear code such as a Reed-Solomon code is described. When the data f1 of a part of data sectors among a plurality of data sectors which form an ECC block F1 having a PO portion q1 formed with a linear code such as a Reed-Solomon code is updated with data f2 to obtain the ECC block F2 having the updated PO portion q2, the ECC block F1+F2 of the exclusive OR of the source data part of the ECC block F1 before updating and the ECC block F2 after updating is taken, so that the XOR of f1 and f2 (i.e. f1+f2) of the data f1 to be updated and the updated data f2 is obtained. The XOR of non-updated data sectors is 0. Then, when the ECC block F1+F2 of the XOR is encoded, the PO portion in the form of the XOR q1+q2 is obtained in accordance with the linearity of the Reed-Solomon code.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: March 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Masayuki Demura, Tetsuya Tamura, Akira Sasaki, Hiroshi Itagaki
  • Patent number: 6348883
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: February 19, 2002
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Patent number: 6304405
    Abstract: A method and apparatus for reducing the amount of time from a power-on status to a ready status of a hard disk drive device. In response to a power-on of a disk drive device, the rotation of a data recording disk is started. The rotational speed of the data recording disk is increased. When it is detected that the rotational speed of the data recording disk reaches an intermediate rotational speed, which is lower than a final rotational speed of the data recording disk, the rotational speed of the data recording disk is fixed at the intermediate rotational speed. One or more control programs recorded on the data recording disk are read and then stored in a memory. Then a ready signal is sent to a host processor. The disk drive device may then receive a read command from the host processor to read data from the data recording disk and to transfer the data to the host processor is detected.
    Type: Grant
    Filed: July 14, 1998
    Date of Patent: October 16, 2001
    Assignee: International Business Machines Corporation
    Inventors: Hideo Asano, Hiroaki Suzuki
  • Patent number: 6292316
    Abstract: A magnetic disk tester which also incorporates a sensor such as an AFM or MFM is described. The device is able directly and quickly to detect and characterize sub-micrometric defects on the surface of magnetic disks. A process for finding and characterizing defects on a magnetic disk according to the invention comprises the steps of rotating the magnetic disk using a spindle motor; writing data on the magnetic disk at selected positions; finding a position on the magnetic disk having a defect which produces an error when reading the data from the magnetic disk; determining coordinates of the defect referenced from an index on the disk; stopping the spindle motor; positioning a sensing device such as an AFM or MFM head over the defect; and sensing characteristics of the defect which aid in determining a cause of the defect.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: September 18, 2001
    Assignee: International Business Machines Corporation
    Inventors: Andreas Dietzel, Friedrich Fleischmann, Frank Krause
  • Patent number: 6275028
    Abstract: In accordance with the present invention, the initialization for orienting the magnetized directions of the free layers of GMR heads (mounted on the diagonally shaded surface of sliders 14) by an external magnetic field is again executed also for the opposite direction, thereby to increase the yield of the GMR heads. Further, it is determined whether the magnetized direction of the pinned layer of GMR heads can be once reversed to the opposite direction, thereby to select damaged GMR heads at an early stage. Then, by performing a reset while performing a quasi-static test for seeing the read back response of the GMR head after restoring the magnetized direction of the pinned layer to a positive rotation, a safe and efficient reset is executed. The reset can be executed not only by applying only a pulse, but also while providing an external magnetic field in the pinning direction, or only by giving a high magnetic field.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: August 14, 2001
    Assignee: International Business Machines Corporation
    Inventors: Takao Matsui, Tatsuya Endo, Hiroaki Suzuki, Kenji Kuroki, Katsushi Yamaguchi, Hideo Asano
  • Patent number: 6259573
    Abstract: A preamplifier circuit to improve the ESD immunity of magnetic recording devices having magnetoresistive (MR) sensors, without degrading the sensor's high-frequency characteristics. The preamplifier circuit is coupled to an MR sensor having one terminal grounded. The preamplifier circuit includes a varistor coupled between a power supply line and a ground terminal. If a high voltage, exceeding the varistor voltage, is applied to the chassis (ground), it is discharged through the varistor between the power supply voltage line and the ground terminal, instead of through the MR head or the arm electronics module. The present invention thereby protects the MR head and the arm electronics module from ESD damage.
    Type: Grant
    Filed: February 22, 1999
    Date of Patent: July 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kazushi Tsuwako, Yoshiro Amano, Takao Matsui, Tsuyoshi Miura
  • Patent number: 6252735
    Abstract: A voltage-biasing, voltage-sensing differential preamplifier having a high input impedance preamplifier circuit to amplify magnetic data readback signals from a magnetoresistive (MR) sensor and feedback circuits to simultaneously hold the electrical center of the MR sensor at a prescribed potential (usually ground) while applying a predetermined constant differential voltage-bias across the MR element. The feedback circuits provide a stable operating point for the MR sensor at the desired bias-voltage, and maintain the average potential on the MR sensor at or near the disk substrate potential to limit the destructive effects of MR sensor contact with conducting asperities.
    Type: Grant
    Filed: February 25, 1999
    Date of Patent: June 26, 2001
    Assignee: International Business Machines Corporation
    Inventors: Paul Wingshung Chung, Stephen Alan Jove
  • Patent number: 6246653
    Abstract: A method and apparatus for reducing the effect of inter-wave interference on signals read from a storage medium and to precisely digitize the read signals are described. An apparatus for digitizing a signal read from a storage medium according to an embodiment of the invention, comprises: a peak detector, for detecting a peak value for an amplitude of a signal read from the storage medium; a threshold value determiner, for employing the peak value obtained by the peak detector to determine a compensation value that is used for compensating for the effect of inter-wave interference on the signal, and for employing the threshold value calculated by the conventional method and the compensation value to determine a compensated threshold value; and a digitization circuit, for digitizing the signal by using the threshold value determined by the threshold value determiner. Optionally an interpolator may be used to obtain more accurate peak values which occur between sample points.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: June 12, 2001
    Assignee: International Business Machines Corporation
    Inventors: Toshio Kanai, Takeo Yasuda, Kazuhiro Tsuruta, Wataru Ichihara
  • Patent number: 6233213
    Abstract: A method and apparatus are described which demodulate channel bits modulated by an arbitrary one of two modulation schemes, by making use of a consolidated reference table with a small address space. The method of the invention comprises the steps of: generating first output bits for representing patterns that correspond to patterns represented by first channel bits other than those patterns being unable to exist under first RLL constraints, the first output bits having a lesser number of bits than the first channel bits; and generating second output bits for representing patterns that correspond to patterns represented by second channel bits other than those patterns being unable to exist under second RLL constraints, the patterns represented by the second output bits being located at discontinuous areas of the patterns represented by the first output bits, the second output bits having a lesser number of bits than the second channel bits.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: May 15, 2001
    Assignee: International Business Machines Corporation
    Inventors: Takenori Okada, Keisuke Tanaka, Teruhiko Ushio
  • Patent number: 6215608
    Abstract: A direct access storage device that (DASD) includes a sector servo control system that controls disk write operations by receiving a servo pattern readback signal in a sector, determining track centering for that sector, and generating a write inhibit signal before any write operations are initiated for that sector. The servo control system is able to make write inhibit decisions without software processing delays, enabling the system to produce a write inhibit signal quickly after an off-track excursion, and to terminate a write inhibit decision quickly after it is no longer needed.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: April 10, 2001
    Assignee: International Business Machines Corporation
    Inventors: Louis Joseph Serrano, Mantle Man-Hon Yu