Abstract: A receiver (FIG. 2 ) for decoding associated compressed video and audio information components transmitted in mutually exclusive "frames" of data with respective time stamps PTS.sub.vid and PTS.sub.aud respectively, includes a controller (216) which is responsive to the respective received time stamps to provide coarse synchronization by delaying or skipping respective frames of one or the other of the components to approximately time align the two components. Fine synchronization is provided by adjusting the processing or clock frequency (215) of the audio signal processor (212) independent of the video processor (214). The control for the frequency adjustment is related to the difference between audio and video time stamps.

Abstract: A rate controlled VBR quantizing system includes a quantizer for quantizing partially compressed video data and further apparatus for monitoring the amount of compressed output data. Dependent upon the amount of compressed output data being lesser or greater than a predetermined value, the quantizer is conditioned to operate in a fixed quantization mode, or a mode wherein only selected blocks of data in respective frames are adaptively quantized, respectively.

Abstract: Video signal compression apparatus includes a memory for storing two fields of image data and providing fields of image data separated by one frame intervals. Image data from corresponding fields of successive frames are subtracted to generate field differences. The field differences are accumulated over respective field intervals, and the sum is compared against a predetermined value. If a sum of differences over a field is less than the predetermined value, the most recent field is considered to be redundant and may be excised. After respective fields are excised, frames of video signal are composed from the remaining fields. The field types (e.g., odd or even) of the fields in the memory are determined, and the data is accessed from the respective fields in memory such that data from odd and even fields occupy odd and even lines in the composed frames respectively.

Abstract: The relationship of a reference current of a current balancing circuit to a first output current at the collector of an output transistor is adjusted via the dimensioning of a first resistance R in the emitter of the output transistor of a current balancing circuit. By adding a second current balancing circuit with a second resistor R' contained therein and which provides a second output current, there results, for R=R', the relationship of the first output current to the second output current corresponding to the relationship of the reference current to the first output current.

Abstract: A hybrid Discrete Cosine Transform (DCT) coder processes blocks of (e.g., 8.times.8) pixels from interlaced or progressive scanned image signals. Processing of image lines by the coder is modified in the presence of image motion to avoid switching between 8.times.8 and 2.times.(4.times.8) transformations. For motion, the lines of two vertically superimposed image blocks are rearranged to produce first and second modified blocks. The modified first block contains pixels from lines in a first field, and the modified second block contains pixels from lines in an associated adjacent second field.

Abstract: In a multi-winding motor of the type which develops switching spikes from respective drive signals, separate interference suppression apparatus is not provided for each motor winding to be triggered, but rather interference suppression circuitry is shared between respective winding drive signal paths. In a first arrangement, a single resistor-capacitor impulse suppression network is commutated between all motor winding connections in predetermined phase relation with the application of drive currents to the respective windings. In a further arrangement, a single impulse suppression circuit is used to cyclically couple the respective low power motor trigger signals to the respective high power winding drive amplifies, which suppression circuit precludes the generation of interference pulses at the interface between the drive circuitry and the motor to be driven.

Abstract: A clocked digital signal processing system includes apparatus for unambiguously indicating the phase of an input signal relative to a reference clock signal. In particular, the disclosed apparatus reduces timing uncertainty between the reference clock, and the output signal of a phase detector representing the phase relationship between the input signal and the reference clock. A phase detector including a logic network provides plural comparison signals representing a phase relationship between the input and reference signals. The comparison signals are conveyed via first and second latch circuits, in respective groups, to a clocked downstream stage. The first and second latch circuits are clocked by different phases of the reference clock and provide outputs synchronous with the reference clock. The downstream stage responds to the reference clock for conveying output signals front the first and second latch circuits to an output at which the unambiguous indication appears.

Abstract: A compression/decompression system includes a source of (1:1 60 Hz) non-interlaced scanned video signal. A preprocessor constructs (2:1 60 Hz) interlaced scanned video signal from the non-interlaced scanned video signal by selection of alternate lines of successive non-interlaced image signals. The interlaced scanned video signal is compressed according to an MPEG protocol of I, P and B frame compression algorithms. I, P and B frame compression is performed such that there are an odd number, greater than one, of B-frames between successive I/P frames (for example the sequence of compressed frames may conform to I, B1, B2, B3, P, B1, B2, B3, P, B1, B2, B3, I, B1, . . . etc). The I compressed frames, the P compressed frames and alternate B compressed frames (the frames B2 in the exemplary sequence) selectively form a primary compressed (2:1 30 Hz) interlaced video signal for reproduction by interlaced scanned receivers. The intervening B-frames selectively form a secondary compressed video.

Abstract: A block of picture elements is DCT transformed and coded to produce a corresponding data block of variable length codewords having an average length. The data blocks are apportioned among fixed length transport blocks as needed to produce full transport blocks. The transport blocks include a direct (DC) component and alternating components at prescribed locations, as well as an address information flag indicating whether or not block data is longer or shorter than the average length, and an address pointer, to facilitate recovery and synchronization of apportioned data blocks at a decoder.

Abstract: A select line scanner for a liquid crystal display includes a plurality of cascaded stages each having an input terminal and an output terminal. Each stage includes a push-pull output circuit including pull up and pull down transistors driven with separate control signals. A further transistor has its conduction path coupled between the control electrode and a point of potential of sufficient value to turn the pull up transistor off. The control electrode of the further transistor is coupled to an output of a succeeding one of the cascaded stages to insure that the output of the respective stage cannot drift to an on state.

Abstract: Variable length codewords representing high definition television image information are processed by a codeword analyzr for prioritizing codewords within a predetermined codeword group. A single FIFO rate buffer conveys codewords subject to analysis to the analyzer. A succeeding codeword group is written into the buffer when a current codeword group is being analyzed, at which time buffer read out is inhibited. In an illustrated embodiment, buffer read out is inhibited, and codeword analysis begins, when MPEG Picture Start or Slice Start codewords associated with the succeeding codeword group approach the buffer output. Buffer read out is enabled at the end of the analysis interval.

Abstract: A method for determining which of pairs of successive video fields have interlace scan characteristics includes generating accumulated differences FD of pixels in successive lines of respective fields of successive pairs of fields and generating accumulated differences FR of pixels in successive lines of interlaced said pairs of fields. The accumulated differences FD and FR are compared and pairs of said fields are classified as interlaced if the ratio of accumulated differences FR/FD is greater than a predetermined threshold value.

Abstract: A variable length encoding/decoding system for use with a layered signal format, and for adaptively providing VLC changes without additional signal overhead, includes a plurality of VLC encoding tables, respective ones of the tables being preprogrammed with VLC codes associated with anticipated signal statistics. The layered signal includes blocks of data subject to common parameters which parameters may be associated with signal statistics. The blocks of data include information indicative of such parameters. Each packet is examined for the common parameter and responsive thereto a default VLC coding/decoding table is assigned. In a further embodiment the VLC table used for each successive codeword is made dependent upon the table utilized for the lastmost codeword and the relative value of the lastmost codeword.

Abstract: Finite impulse response (FIR) filter circuitry for processing time division multiplexed sampled signals includes parallel sets of delay elements, for delaying respective signals to be filtered, each set having a plurality of taps. Corresponding taps of the respective sets of delay elements are coupled to common weighting and summing structure. A time division multiplexed signal is coupled to the parallel sets of delay elements, respective sets being exclusively clocked on the occurrence of corresponding signals.

Abstract: A compression/decompression system includes a source of non-interlaced scanned video signal. A preprocessor constructs interlaced scanned video signal from the non-interlaced scanned video signal by selection of alternate lines of successive non-interlaced image signals. The interlaced scanned video signal is compressed according to known methods to generate primary compressed video data. The primary data is decompressed by known processes, inverse to the compression processes, to regenerate the interlaced scanned frames. Interlaced scanned video signal, corresponding to the intervening lines of the non-interlaced scanned video signal, which were not included in the primary interlaced scanned video signal, is predicted from the decompressed frames of video signal. In addition the intervening lines of the original non-interlaced scanned video signal, which were not included in the primary interlaced scanned video signal, are formed into secondary interlaced scanned video signal.

Abstract: A VLSI integrated circuit, which comprises a single IIR input and global section and identically-structured cascadable filter sections, each of which filter sections includes a pair of time-multiplexed, real-coefficient, input-weighted FIR filter units and additional delay means, can be selectively programmed to operate in any one of a number of different filter configurations that can define real FIR or IIR filters, complex FIR or IIR filters, or filters which are various combinations thereof. One or more of such integrated circuits are useful for implementing a digital deghosting and/or equalization filter.

Abstract: In a video signal processing system, a single adaptive passband equalizer is used to process a composite Quadrature Amplitude Modulated (QAM) signal encoded with high priority (HP) and standard priority (SP) components. The equalizer output is phase corrected by a de-rotator, and filtered to separate the HP and SP components. Error signals respectively representing HP and SP phase errors are developed. One of the error signals controls the operation of the de-rotator. Both error signals are used to generate updated coefficients for the adaptive equalizer. Afterwards the HP and SP components are decoded and combined.

Abstract: For transmission of coded picture data, coded data may be arranged in blocks having a predetermined average length. Blocks which are not full are filled with data from other blocks. To support decoding in the presence of interference, each of the blocks additionally contains an address pointer which points to addresses in a decoder memory from which data separated from blocks having a greater than the average word length are reconstituted and used for decoding. The additional address pointer information, for a constant channel capacity, results in a lower data rate for picture data, which may lead to reduced picture quality during undisturbed decoding. Respective recovery pointer pairs having full word width are inserted between a predetermined number of data blocks, whereby other address pointers only cover the Least Significant Bits having full word width. Accordingly, additional data can be inserted into the data stream.

Abstract: A television signal receiver processes a television signal representing a letterbox image display format with a main image region, and a bar region containing auxiliary information to help convert from interlaced to progressive scanning. The auxiliary information is processed in a signal path including a nonlinear amplitude expander and apparatus for modifying the operation of the signal path as a function of the noise content of the television signal.

Abstract: The process disclosed enables the "time domain aliasing cancellation" method to be extended systematically to larger block overlapping. The boundary conditions which, when using various modified transforms, the analysis and synthesis windows must comply with, can thus be given. The transform series must also be included in the design of each analysis and synthesis window in order to optimize for a given application, because this changes the boundry conditions with which an analysis window function can be determined. Design for analysis and synthesis windows have shown that analysis and synthesis properties obtained by multiple block overlapping are significantly better than those obtained by convential double block overlapping. The systematic method of the invention offers numerous possibilites for optimizing windows in special applications.