Abstract: A self-aligned metal electrode sensor structure. The self-aligned metal electrode sensor structure includes a substrate which includes electronic circuitry. An interconnect structure is formed adjacent to the substrate. The interconnect structure includes conductive interconnect vias which pass through the interconnect structure. A sensor is formed adjacent to the interconnect structure. The sensor includes a pixel metallization section and a doped layer electrode. The pixel metallization section is electrically connected to the interconnect via. The pixel metallization section includes an outer surface which is substantially planar. The doped layer electrode includes an inner surface adjacent to the outer surface of the pixel metallization section. The entire inner surface of the doped layer electrode is substantially planar. A transparent conductive layer is formed adjacent to the sensor. The interconnect via and the transparent conductive layer electrically connect the electronic circuitry to the sensor.

Abstract: A program for monitoring computer system performance includes a collection of source code modules in the form of a high level language. Each of the source code modules is compiled into a corresponding object code module. The object code modules are assembled into machine dependent code. The machine code is translated into a program module in the form of a machine independent register translation language. The program module is partitioned into basic program components. The basic program components include procedures, basic blocks within procedures, and instructions within basic blocks. Fundamental instrumentation routines identify, locate, and modify specific program components to be monitored. The modified basic program components are converted to an instrumented machine executable code to be executed in the computer system so that performance dam can be collected while the program is executing in the computer.

Abstract: An apparatus is provided for detecting the signaling frequency of communications signals transported on the trunk and lobe circuits of a token ring. The communications signals including Differentially Manchester Encoded data signals. The apparatus includes an internal trunk circuit and a plurality of ports including an input port for connecting to an input trunk segment, and an output port for connecting to an output trunk segment, and a plurality of lobe ports for connecting to the lobe circuits. Means are provided for sensing the frequency of the data signals at each of said plurality of ports. The sensing means including means for taking multiple successive timing samples, and grouping the samples into quality groups.

Abstract: In an interactive video-on-demand system, real-time programs are encoded as a transport stream including a plurality of transport stream packets. Some of the transport stream packets include timing signals indicating the real time of the program. The transport stream packets are formatted into transport cells for transport over an asynchronous transfer mode network from a source to a destination. The cells are transported at a transport rate which is determined by a network clock. The transport rate is chosen to deliver the transport stream faster than the real time of the program. While transporting the transport stream, it is determined if the transport stream is being transported ahead of the real time of the program. In this case, idle cells are injected into the transport stream to have the program arrive at the destination in the real time of the program.

Abstract: An apparatus for establishing timing signals of a communications network includes a plurality of ports and an internal trunk circuit for interconnecting trunk segments and lobes of the network. A speed detection circuit connected to each of said plurality of ports, are provided for sensing a plurality of timing signals, there being one timing signals sensed at each of the plurality of ports. The apparatus establishes a timing signal on the internal trunk equal to the timing signal senses at a majority of the ports to enable a majority of the nodes connected to a majority of the plurality of lobe ports to transport communications signals via the network.

Abstract: In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays experienced by the digital signals are measured as a delay value relative to a reference clock signal propagated through a second signaling path duplicating the delays of the first signaling path. The delay value is used to selectively delay the digital signal to maintain a fixed relationship between the transmitted and received digital signals. Delay measuring and regulation is provided by driving the reference and digital signals through comparable tapped delay lines, the output taps of a measuring delay line controlling the output taps of a delaying line. Storage latches are provide to hold the measured delay value stable between successive samples.