Abstract: A simple lightweight apparatus for sensing excessive contamination on the faces of an array of light or infrared detectors comprises mounting a light or infrared-emitting diode near one or more of the detectors. When the diode is energized, the associated detectors should detect its radiation, thereby indicating that the detector is operable and that contamination is not excessive.

Abstract: A device having a light emitter coupled to direct light to a portion of a photodetector to provide Built-In Test Equipment (BITE) capability for an optical sensor. A light emitting diode and a photodiode are mounted side by side on the upper surface of a conventional header with suitable electrical connections bonded thereto. A prismatic light bridge member overlies the light emitting diode and extends to cover a portion of one corner of the photodetector. This member serves as a light conduit, directing virtually all of the light from the emitter to the detector by virtue of the near total internal reflection of the surfaces of the light conduit member. An outer enclosure having a transparent glass window serves to seal and protect the respective elements while permitting external radiation to reach the photodetector.Alternative embodiments provide for coupling of light from a single emitter or a plurality of emitters to a single associated photodetector.

Abstract: A semiconductor photoconductor having low impedance nonmetallic contacts is disclosed which has increased detectivity over prior art photoconductor structures. The improved photoconductor has metallic contacts that are separated by a contact length that is greater than the optical length of the detector. The contact regions of the semiconductor adjacent the detector region are thicker than the detector region. The process for fabricating the photoconductor includes thinning the detector region to an appropriate thickness while preserving the greater thickness of the contact regions.

Abstract: Carbon fibers in a carbon-fiber-reinforced metal-matrix composite having a relatively very high modulus are treated with a relatively thin amorphous carbon coating precedent to a metal-oxide film to improve the adhesion thereof to the carbon fiber thereby facilitating the wetting of carbon fibers to molten matrix metal.

Abstract: A carbon fiber reinforced metal matrix composite is produced by metal oxide coating the surface of the fibers by passing the fibers through an organometallic solution followed by pyrolysis or hydrolysis of the organometallic compounds. The metal oxide coated fibers so produced are readily wettable without degradation when immersed in a molten bath of the metal matrix material.

Abstract: A method of making a narrow gate MESFET including the steps of placing a layered mask of nitride and polysilicon over a channel region for self-aligning in a substrate, oxidizing and then removing the polysilicon to reduce the remaining polysilicon width, etching the nitride to the polysilicon width, oxidizing the substrate where the nitride defines the gate therein, removing the nitride, and depositing metal on the gate to form the MESFET Schottky gate. Advantages of the improved MESFET include a relatively higher device gain, greater IC density, a self-aligned Schottky gate, controllable minimum series resistance, a relatively short channel using a conventional photo process, and a n- resistor that may be easily simultaneously fabricated therewith.

Abstract: A split gate VMOSFET having an enhancement transistor and a depletion load transistor on opposing sidewalls of a V-groove region. In the process, a differential oxidation rate due to the different crystal orientations of the substrate is used to complete device fabrication in a relatively simple manner. The resultant process steps make it possible to fabricate a VMOSFET having symmetrical geometry in which a transfer gate can be easily implemented.

Abstract: For use in a microprocessor on a single semiconductor chip, a circuit responsive to first and second non-overlapping time signals for removing timed delay in a first data line. A first enhancement-type field effect device has its drain coupled to the first data line and its gate providing an input for the first timing signal. A second enhancement-type field effect device has its drain coupled to the source of the first device and its source coupled to a source voltage. The source voltage is at ground potential. A third enhancement field effect device has its drain coupled to the first data line, its source coupled to the gate of the second device, and its gate providing an input for the second timing signal.

Abstract: A mask programmable logic array (PLA) for producing a particular digital output given a certain digital input. The input signals to the PLA first pass through a series of AND gates resulting in a predetermined number of product terms being formed. The product signals then pass through a set of OR gates to become the final output signals. In the subject invention, the AND gates and OR gates are implemented through the use of NOR-NOR logic. A first set of NOR gates is implemented in an array to receive input signals and to produce product terms. A second and third set of NOR gates form two arrays. These two arrays are then located on either side of the first array to receive selected product signals in order to produce final output signals. In effect the OR portion of the PLA has been split into two arrays.

Abstract: A method and apparatus for bit manipulation in a digital processor being suitable for executing a plurality of instructions stored in a memory and carried from said memory in accordance with a plurality of machine cycles, each of said instructions including an operational code. A decoder generates a bit mask in response to an operational code. The bit mask generated is in binary digits which are the complement of 2.sup.i where i is the number in base 10 represented by the three least significant bits of the operational code. A register stores the particular bit-mask. An additional register stores a word in which a bit is to be manipulated. Logic circuitry performs one or more logic operations on the output of the registers whereby a desired bit in said word is manipulated. The output of the logic circuitry may be tested and depending on the result, a jump to a particular instruction stored in the memory may be made.

Abstract: A high frequency FET having a channel region and wherein said channel region contains an implant, said implant having a first dosage concentration at a first distance from the gate of said FET and a second dosage concentration at a second distance from the said gate and wherein said first distance is larger than said second distance and said first dosage concentration is larger than said second dosage concentration.

Abstract: A split gate V groove FET device mounted in a substrate with a first terminal comprising a body of a first conductive material in the apex of said V groove, said first terminal connected to a first conductive channel in a first side of said V groove to form a first transistor and said first terminal connected to a second conductive channel in a second side of said V groove to form a second transistor.

Abstract: The chip topography of an MOS microprocessor chip. The chip architecture includes an internal data bus and an internal address bus. Input/output circuitry is located along the top edge of the chip and is coupled to the data bus. Output circuitry is located along the bottom edge and coupled to the address bus. A program storage area which includes a ROM is located in the lower left hand corner of the chip. The ROM contains instruction words for defining the operation of the microprocessor. A data storage area which includes a RAM is located in the upper left hand corner of the chip and is coupled to the data bus. An ALU area is located to the right of the data storage area and is coupled to the data bus for performing arithmetic and logic operations on data. A condition decode ROM located in the approximate center of the chip is coupled to the data bus and is used for decoding a condition field of an instruction word received from the ROM.

Abstract: For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type field effect devices are connected in series with the drain of the first device being connected to the data line and the source of the second device being connected to a source voltage. The gate of one of the field effect devices provides an input for the timing signal. The gate of the remaining field effect device provides an input for the data signal. A depletion-type field effect device has its source and gate coupled to the series connection point and its drain connected to a drain voltage source. The depletion-type field effect device prevents a charge redistribution from the data line to the series field effect devices when these devices are not discharging the line.

Abstract: An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto.

Abstract: In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof.

Abstract: An automatic exposure system for a copying machine comprising a scanning optical system having an imaging period and a calibrating period, including a lamp illumination control loop for providing a calibrated control signal, said control loop comprising means for supplying a reference control signal to the lamp means during the calibration period, a multiplying digital to analogue convertor arranged to respond to the output of a light intensity detector positioned to receive light reflected during the calibration period from a document to be copied, a comparator for comparing the output of the digital to analogue convertor and the reference control signal and for controlling the countdown of a digital counter to equalize the convertor output and reference control signal, and circuit means for maintaining said counter output constant during a subsequent imaging period and for supplying a predetermined input to the digital to analogue convertor to generate as its output said calibrated control signal.

Abstract: A random access memory (RAM) containing 256 memory cells organized as two pages, each page containing 16 8-bit wide working registers. RAM row address circuitry as well as read-write and page-select circuitry are provided. A fixed transistor static RAM cell is used as the memory cell. Double rail transfer of data is employed. The memory cells and bit lines associated with each of the two pages is interweaved in the array so that the precharged circuitry and the RAM input/output circuitry associated with each of the pages is alternately configured on the chip.

Abstract: A controller for directing a host machine which is operative to include a central processor for program execution, a system bus controlled by the central processor for carrying data, address and control signals, and a data memory coupled to the system bus. Additionally included is a direct memory access moudle for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update.

Abstract: In a control module having a central processor coupled through a system bus including data, address and control lines to access a data memory, a direct access apparatus is included coupled through the system bus to request a hold of the central processor and upon acknowledgement for directly accessing the data memory through the system bus for directing the control registers of a host machine. Also included are a diriment element interfaced to the central processor for receipt of control signals on the system bus from the direct access apparatus for hold request and for transmission of first and second control signals on the system bus from the central processor for acknowledgement, and a timed protocol unit for supervising the data, address and control signals transported on the system bus.