Abstract: This invention is a method for extending the coverage and/or improving the capacity of wireless communication networks comprising inserting a Relay Node (RN) in the Radio Access Network (RAN). The relay node relays the signal between the Base Station node (eNB) and the User Equipment (UE). The relay node is wirelessly connected to the base station. The base station uses the same radio access technology (RAT) for the base station to user equipment link and the base station to relay node link. The relay node uses the same radio access technology for the base station to relay node link and the relay node to user equipment link. The relay node is non-transparent and seen as base station by the user equipment.

Abstract: An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.

Abstract: System for ultra-wideband communications providing high data rates over an extended operating range in the presence of interferers. A preferred embodiment comprises an ultra-wideband (UWB) device that makes use of a portion of the UWB frequency range to help provide good performance in the presence of interferers. Additionally, since only a portion of the UWB frequency range is used, multiple devices can simultaneously transmit and receive by using different portions of the UWB frequency range.

Abstract: An analog-to-digital converter (“ADC”, 40) comprising an input (VIN2) for receiving an input analog voltage. The ADC further comprises a digital-to-analog circuit, comprising a meandering string (12′) of series connected resistive elements (R0′-R14′) having a plurality of voltage taps (T0′-T15′), as well as a number of bit lines (BL0′-BL3′) and a number of word lines (WL0′-WL3′). For a given input analog voltage, the given input analog voltage is closest to a voltage at a selected one of the plurality of taps. In addition, the selected one of the plurality of taps is associated with one of the number of bit lines and one of the number of word lines. Additionally, the ADC further comprises a flash circuit (44, 46, 48, 50, 42, CAT0′-CAT3′) coupled to receive the input analog voltage from the input and in response to identify either the one of the number of bit lines or the one of the number of word lines.

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWL1L). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).