Patents Represented by Attorney, Agent or Law Firm Ronald P. Kananen
  • Patent number: 6818986
    Abstract: An IC (semiconductor device) comprises a package substrate provided on its face side with a plurality of wiring patterns such as electrode lands and wirings and provided on its back side with a plurality of electrode bumps corresponding to the wiring patterns, an IC chip mounted on the face side of the package substrate in a face-up manner, a sealing resin sealing the IC chip, and an indication provided on the back side of the package substrate for indicating the position of the IC chip. A method of inspecting a failure reason in the case of some failure of the IC chip comprises the steps of forming an opening by removing from the back side the package substrate in the region surrounded by the indication, mounting the IC chip on a test substrate, passing an electric current to the IC chip for operation, and inspecting and analyzing the reason of failure by a photo-emission analyzing method.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: November 16, 2004
    Assignee: Sony Corporation
    Inventors: Yuichiro Ikenaga, Yasushi Otsuka
  • Patent number: 6815240
    Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provide, by at first preparing a manufacturing substrate having a characteristic of being capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic of being suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventor: Hisao Hayashi
  • Patent number: 6816095
    Abstract: A high speed, high accuracy parallel/serial conversion circuit, wherein a PLL circuit 50 receives as input and locks a clock CLK, and supplies the same to different parts of an apparatus; the PLL circuit 50 controls a 16-tap ring oscillator 60 to shift the phase of a clock frequency-locked to a reference clock so as to generate 32 types of phase shift pulses CK0 to CK31 shifted in phase by increments of {fraction (1/32)} of the clock width from the reference clock by the differential outputs of the 16 taps and supplies the same to a P/S conversion circuit 70; and the P/S conversion circuit 70 generates fine width pulses with {fraction (1/32)} pulse widths based on the 32 types of phase shift pulses shifted in phase by increments of {fraction (1/32)}. Further, the fine width pulses are used to convert parallel signals output from a RAM 30 and a decoder 40 to a serial signal.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventors: Koichi Yokoyama, Katsunori Sato
  • Patent number: 6816395
    Abstract: The present invention provides a switching power supply which includes a main rectifying and smoothing circuit (40) and a secondary rectifying and smoothing circuit (50) for rectifying and smoothing an output obtained at a secondary coil (22) of a converter transformer (20) whose primary coil (21) is supplied with a switching output from a switching element (30) which switches a direct input.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventors: Katsumi Kobori, Masami Okada
  • Patent number: 6816415
    Abstract: An additional information read/write system has an ID/additional information distributing apparatus, an ID postscribing apparatus, and a drive system. The ID/additional information distributing apparatus includes a managing unit for managing IDs postscribed to optical discs and additional information for updating content read from each of the optical discs and a distributing unit for distributing the IDs and the additional information corresponding to the IDs. The ID postscribing apparatus includes a transmitting and receiving unit and a writing unit. The drive system includes a transmitting and receiving unit for transmitting the IDs to the ID/additional information distributing apparatus and receiving the additional information, a writing unit for writing the additional information on a storage medium, and a playback unit for playing back the content updated based on the additional information from the storage medium.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: November 9, 2004
    Assignee: Sony Corporation
    Inventors: Koichi Nakajima, Yoriaki Kanada, Akie Sugiyama, Toru Aida
  • Patent number: 6813778
    Abstract: A method and system manages and controls the download of programming, i.e., code objects, to a set-top terminal connected to a cable television system so as to prevent disruptions to service that may arise if only some of the objects specified are successfully downloaded and might, therefore, function improperly or conflict with existing applications. When the message to download new or additional code objects lists two or more objects to be acquired, the set-top terminal will only enable and execute downloaded objects if all the listed objects are successfully acquired. If only some of the objects the terminal has been instructed to download are acquired, those downloaded objects may either be purged or stored in memory without being enabled and executed. The system operator may specify in the message instructing the terminal to acquire new objects, whether the listed objects must be implemented as a group or not at all.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: November 2, 2004
    Assignee: General Instruments Corporation
    Inventors: Christopher Poli, Douglas S. Makofka, Ira S. Lehrman, Christopher S. Del Sordo, Thomas F. Bates, IV
  • Patent number: 6811630
    Abstract: An ultrasonic vibration method and an ultrasonic vibration apparatus, which do not have a directional property in the direction of vibrations, are disclosed. A pair of ultrasonic horns (11), (12), each having an ultrasonic vibrator (13), (14) provided at an end portion thereof, are disposed in an intersecting relationship to each other, and the composite vibrations of transverse vibrations produced by the pair of ultrasonic horns (11), (12) when the other ultrasonic horns (12), (11) are excited to generate longitudinal vibrations are extracted at the intersecting point of the pair of horns (11), (12) and applied to a contact object member through a presser (22).
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: November 2, 2004
    Assignee: Sony Corporation
    Inventors: Morio Tominaga, Shinji Iwahashi
  • Patent number: 6812133
    Abstract: The present invention comprises the steps of forming a connection hole in an interlayer insulating film including an organic insulating film; forming an inorganic film covering on an upper surface of the interlayer insulating film and an inner surface of the connection hole; forming an organic film for filling inside the connection hole on an inorganic film; removing the organic film inside the connection hole so as to leave a part of the organic film at a bottom of the connection hole; forming a wiring trench connecting to the connection hole in the interlayer insulating film; removing the organic film inside the connection hole; removing the inorganic film; and forming a trench wiring by filling a conductive material in the wiring trench and inside the connection hole and forming a plug continuing from the trench wiring.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: November 2, 2004
    Assignee: Sony Corporation
    Inventor: Koichi Takeuchi
  • Patent number: 6808999
    Abstract: A bipolar transistor has a high performance and high reliability, which are obtained by enhancing a withstanding voltage between an emitter and a base. The bipolar transistor includes a first impurity diffusion layer in a semiconducting substrate, an opening disposed in the first conductive film. A third impurity diffusion layer is formed so as to contain the second diffusion layer and side walls are formed on the side walls of the opening. A fourth impurity diffusion layer in the third impurity diffusion layer is formed in the opening surrounded by the side walls.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: October 26, 2004
    Assignee: Sony Corporation
    Inventor: Hiroyuki Miwa
  • Patent number: 6805973
    Abstract: A method for producing an aluminum nitride/aluminum base composite material comprising the steps of; (A) charging aluminum nitride powder into a container provided in a molten metal pressure apparatus, (B) applying pressure to the aluminum nitride powder in the container, (C) pouring a molten aluminum base material into the container, and, (D) applying pressure to the molten aluminum base material in the container to fill the aluminum base material in space between the aluminum nitride powder particles.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: October 19, 2004
    Assignee: Sony Corporation
    Inventors: Shingo Kadomura, Kei Takatsu, Shinsuke Hirano, Nobuyuki Suzuki
  • Patent number: 6804074
    Abstract: A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: October 12, 2004
    Assignee: Sony Corporation
    Inventors: Norio Shoji, Junkichi Sugita, Kimimasa Senba, Toshihiro Kawakubo
  • Patent number: 6803918
    Abstract: An image processing apparatus capable of performing flexible, high speed processing, wherein a memory region emptied due to a change of display resolution can be used as a texture memory, increase of an overhead such as switching pages can be prevented, and a decline in the performance is not caused. A built-in DRAM inside a semiconductor chip has a configuration for storing display data and the texture data required by at least one graphic element. The texture data can be stored in portions other than the display regions, so the built-in DRAM can be used efficiently and an image processing apparatus achieving both high speed operation and a reduction of power consumption can be realized.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: October 12, 2004
    Assignee: Sony Corporation
    Inventors: Mutsuhiro Ohmori, Toshio Horioka
  • Patent number: 6801388
    Abstract: A spindle motor having a rotor R and a stator S. The stator S comprises a stator housing 80, a first bearing 82, a second bearing 84, a stator yoke 86, and a drive coil 88. The first bearing 82 is held in the stator housing 80 and supports a shaft 60, allowing the shaft 60 to rotate. The second bearing 84 provided between the stator housing 80 and a rotor housing 50, arranged concentric to the first bearing 82 in a radial direction, and supporting a rotor R, allowing the rotor R to rotate. The stator yoke 86 is formed integral with the stator housing 80, constituting a part of a housing 2 containing the rotor R and the stator S, and is made of magnetically permeable material. The drive coil 88 mounted on the stator yoke 86 and arranged in face-to-face relation with the drive magnet 58.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: October 5, 2004
    Assignees: Sony Corporation, Nippon Keiki Works, Ltd.
    Inventors: Shun Kayama, Hidetoshi Shinozawa
  • Patent number: 6799589
    Abstract: In the art of wet-cleaning a substrate by etching with a cleaning solution prepared by dissolving hydrofluoric acid as an active component in water, using the process of measuring the concentration of a predetermined component regularly and then replenishing the cleaning solution with a component for correcting the concentration at need on the basis of the result of measurement on the concentration in case of cleaning the substrate with an aqueous solution of ammonium fluoride as the cleaning solution while controlling air in a cleaning draft at an exhaust rate within a predetermined range.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: October 5, 2004
    Assignee: Sony Corporation
    Inventor: Yasuhito Inagaki
  • Patent number: 6801074
    Abstract: A clock switching circuit is provided for switching from a first clock signal being output to a freely selected second clock signal among a plurality of clock signals having different frequencies and phases while preventing generation of a hazard. The switching circuit has a plurality of unit circuits for respectively receiving as an input the clock signals, selection signals of the clock signals and enabling signals and controls supplying and stopping of the clock signals in accordance with the selection signals and the enabling signals. A feedback circuit monitors output conditions of the plurality of unit circuits and, when outputting of all clock signals of the plurality of unit circuits was stopped as a result of stopping the first clock signal, giving a plurality of the unit circuits the enabling signal for approving starting of a supply of the second clock signal.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: October 5, 2004
    Assignee: Sony Corporation
    Inventor: Tetsumasa Meguro
  • Patent number: 6800527
    Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op
    Type: Grant
    Filed: February 14, 2003
    Date of Patent: October 5, 2004
    Assignee: Sony Corporation
    Inventors: Yoshiaki Hagiwara, Hideaki Kuroda, Michitaka Kubota, Akira Nakagawara
  • Patent number: 6798451
    Abstract: A solid-state image pickup device including a matrix of unit pixels, each unit pixel including five transistors, a plurality of horizontal signal lines wired on a row-by-row basis and a vertical signal line commonly wired for the plurality of the horizontal signal lines. A reset transistor resets a floating diffusion region FD, and the reset level of the reset transistor is output to the horizontal signal lines through an amplifying transistor. In succession, a signal charge of a photodiode is read out into the floating diffusion region FD through a read out transistor, and the signal level based on the signal charge is output to the horizontal signal lines through the amplifying transistor.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: September 28, 2004
    Assignee: Sony Corporation
    Inventors: Ryoji Suzuki, Takahisa Ueno, Koichi Shiono, Kazuya Yonemoto
  • Patent number: 6796427
    Abstract: A tape cassette storing case for storing a tape cassette comprises a cubic body with lateral walls, a lid body with lateral walls, and a junction member constituting one of the lateral walls of the lid body in linkage with the cubic body and the lid body via hinging means; and a pair of cylindrical members are vertically disposed on a bottom plate of the cubic body by way of being idly inserted in hub holes of a tape supplying and tape take up reel; wherein each of the hub holes comprises a driving pawl hole having an inner peripheral surface formed with a reel-driving pawl, and a reference hole that is formed in concentricity with the driving pawl hole and provided with a diameter smaller than that of the driving pawl hole; and the pair of cylindrical members are respectively formed to be of a height enough to arrive at the reference hole.
    Type: Grant
    Filed: September 27, 2001
    Date of Patent: September 28, 2004
    Assignee: Sony Corporation
    Inventors: Hiroyuki Kiso, Takatsugu Funawatari
  • Patent number: 6798581
    Abstract: An optical pickup apparatus, in which the quantity of light incident to an aperture diaphragm of an objective lens and the “rim intensity (RI)” are maintained constant even when a spherical aberration is corrected by passing a light beam through an expander lens unit before it reaches the objective lens, and which is able to adequately read/write information signals from/to optical recording media, and a read/write apparatus which includes the optical pickup apparatus are provided. The expander lens unit includes a first lens group and a second lens group, and is disposed such that a focal position of the second lens group, which is closer to the objective lens than the first lens group, is on the aperture diaphragm of the objective lens.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: September 28, 2004
    Assignee: Sony Corporation
    Inventors: Kenji Yamamoto, Kiyoshi Osato, Yoshiaki Kato
  • Patent number: 6797571
    Abstract: The present invention provides a method of manufacturing a semiconductor device, in which while a conductive layer is formed on an oxide film formed as an insulating layer by using a CVD method, oxygen deficiency of the oxide film can be avoided without any drop in an dielectric breakdown resistance as the insulating layer of the oxide film and without any reduction in a long-term reliability. In this manufacturing method, when the conductive layer as a gate electrode is formed on the oxide film formed as a gate insulating layer, the conductive layer is formed in a non-reducing atmosphere.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: September 28, 2004
    Assignee: Sony Corporation
    Inventors: Kojiro Nagaoka, Masaki Saito