Abstract: An interactive television program guide system is provided in which the program guide may provide the user with a selectable list of combination categories. Combination categories are composed of multiple simple categories such as sports, news, comedy, movies, children, etc. Program listings are supplied to the program guide. At least some of the program listings are associated with combination categories. A combination category build process may be used to assign combination categories to program listings. The user is able to use the selectable categories list to quickly identify programming of interest.
Type:
Grant
Filed:
August 31, 2009
Date of Patent:
January 18, 2011
Assignee:
United Video Properties, Inc.
Inventors:
Edward B. Knudson, Joel G. Hassell, Michael D. Ellis, William L. Thomas
Abstract: Laser lit flat panel displays are disclosed including edge-lit and direct lit backlights. In certain embodiments, laser assemblies are selected to obtain bandwidth distributions to reduce speckle.
Abstract: Embodiments of the knee brace disclosed herein provide a combination of external ligament support and/or relief from pain caused by osteoarthritis with patellofemoral support. The brace includes a rigid frame and a flexible strap configured to extend across the wearer's patella to provide anterior loading thereto. The strap is operatively secured at either end to components of the rigid frame, thereby providing maximum leverage for applying force to the wearer's patella. In some embodiments, the strap includes a removable and adjustable buttress for directly contacting the wearer's patella. The patellar strap provides dynamic loading to the patella through the wearer's range of motion for relief of patellofemoral dysfunction, such as patellar shift, subluxation and dislocation, and malalignments such as patella alta, patella baja, tilt and glide.
Type:
Grant
Filed:
September 28, 2006
Date of Patent:
January 11, 2011
Assignee:
DJ Orthopedics, LLC
Inventors:
Andy Kazmierczak, John Martin, Richard E. Gildersleeve, John Fulkerson, Kurt Jacobson, Scott Seligman
Abstract: The present invention relates to novel human antibodies specifically directed against human immunoglobulin E (anti-IgE). The present invention also relates to pharmaceutical compositions and methods for treating asthma, in particular allergic asthma, as well as other IgE-mediated disorders including allergic rhinitis and food allergies.
Type:
Grant
Filed:
April 1, 2008
Date of Patent:
January 11, 2011
Assignees:
Amgen Fremont Inc., Pfizer Inc.
Inventors:
Wai Liu, Mike Yeadon, Isabelle de Mendez, Alison Logan, Gerald F. Casperson, Arvind Rajpal, Mark A. Moffat, Wei Liao, Caroline Brown, Nurten Beyaz-Kavuncu, Judith Diaz-Collier, Sirid-Aimee Kellermann
Abstract: Hypoxia, a state of lower than normal tissue oxygen tension, has recently been implicated in a host of human diseases, including cancer, heart disease, and neurological disorders. Novel associations between p97 and other proteins, including UBX-domain-containing proteins (UBX-polypeptides), HIF1?, and a variety of E3 ligases are provided herein. The disclosure provides complexes comprising UBX-domain-containing polypeptides (UBX-polypeptides) and other polypeptides involved in the degradation of ubiquitinated proteins. In addition, the disclosure provides uses for active agents that modulate protein-protein complex formation between an UBX-polypeptide and its complementary-binding substrate. For example, the disclosure provides methods for treating or preventing hypoxia-related disorders or conditions in a patient or a cell by administration of an active agent that modulates the activity of an UBX-polypeptide and/or its complementary binding-substrate.
Type:
Grant
Filed:
November 5, 2008
Date of Patent:
January 11, 2011
Assignee:
California Institute of Technology
Inventors:
Gabriela Alexandru, Raymond Deshaies, Johannes Graumann
Abstract: Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements (“HLEs”), each of which can provide a portion of the full functionality of an FPGA logic element (“LE”). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.
Type:
Grant
Filed:
May 7, 2007
Date of Patent:
January 11, 2011
Assignee:
Altera Corporation
Inventors:
Kar Keng Chua, Sammy Cheung, Hee Kong Phoon, Kim Pin Tan, Wei Lian Goay
Abstract: Phase locked loop circuitry operates digitally, to at least a large extent, to select from a plurality of phase-distributed candidate clock signals the signal that is closest in phase to transitions in another signal such as a clock data recovery (“CDR”) signal. The circuitry is constructed and operated to avoid glitches in the output clock signal that might otherwise result from changes in selection of the candidate clock signal. Frequency division of the candidate clock signals may be used to help the circuitry support serial communication at bit rates below frequencies that an analog portion of the phase locked loop circuitry can economically provide. Over-transmission or over-sampling may be used on the transmit side for similar reasons.
Abstract: A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.
Abstract: An interactive television program guide system is provided. An interactive television program guide provides users with an opportunity to select programs for recording on a remote media server. Programs may also be recorded on a local media server. The program guide provides users with VCR-like control over programs that are played back from the media servers and over real-time cached copies of the programs. The program guide also provides users with an opportunity to designate gift recipients for whom programs may be recorded.
Type:
Grant
Filed:
August 20, 2007
Date of Patent:
January 11, 2011
Assignee:
United Video Properties, Inc.
Inventors:
Michael D. Ellis, William L. Thomas, Thomas R. Lemmons
Abstract: An electronic program schedule system with product ordering capability which includes a data processor for receiving program schedule information for a plurality of programs, and a user control apparatus, such as a remote controller, for generating user control commands and transmitting signals to the data processor in response thereto. The television program schedule information is displayed on a display apparatus such as a television receiver. A video display generator receives video control commands from the data processor and program schedule information and displays a portion of the program schedule information on the receiver. The program schedule information indicates the availability of a product or service for certain of the programs included in the program information, wherein the product or service is associated with the program, such as a program transcript or videocassette.
Type:
Grant
Filed:
March 14, 2003
Date of Patent:
January 11, 2011
Assignee:
United Video Properties, Inc.
Inventors:
Michael D Ellis, Bruce Davis, Edward B Knudson, Larry Miller
Abstract: In certain embodiments, this present invention provides polypeptide compositions, and methods for inhibiting Ephrin B2 or EphB4 activity. In other embodiments, the present invention provides methods and compositions for treating cancer or for treating angiogenesis-associated diseases.
Abstract: A programmable logic device is programmed to perform arithmetic operations in an internal format that, unlike known standard formats that store numbers in normalized form and require normalization after each computational step, stores numbers in unnormalized form and does not require normalization after each step. Numbers are converted into unnormalized form at the beginning of an operation and converted back to normalized form at the end of the operation. If necessary to avoid data loss, a number may be normalized after an intermediate step.
Abstract: A programmable logic device integrated circuit (“PLD”) includes high-speed serial interface (“HSSI”) circuitry in addition to programmable logic circuitry. The HSSI circuitry includes multiple channels of nominal data-handling circuitry (typically including clock and data recovery (“CDR”) circuitry), and at least one channel of nominal clock management unit (“CMU”) circuitry (typically including phase-locked loop (“PLL”) circuitry or the like). To increase the flexibility with which the channels can be used, the nominal data-handling channels are equipped to alternatively perform CMU-type functions, and the nominal CMU channel is equipped to alternatively perform data-handling functions.
Type:
Grant
Filed:
March 19, 2007
Date of Patent:
December 28, 2010
Assignee:
Altera Corporation
Inventors:
Sergey Shumarayev, Wilson Wong, Tim Tri Hoang, Thungoc M. Tran
Abstract: Replication-competent adenoviral vectors which selectively replicate in cancer cells are provided. The replication-competent viral vectors comprise an E2F responsive promoter and/or a telomerase promoter operatively linked to an adenoviral coding region. The replication-competent adenoviral vectors effectively replicate in a variety of types of cancer cells and find broad utility in the treatment of cancer.
Abstract: An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.
Type:
Grant
Filed:
March 17, 2005
Date of Patent:
December 28, 2010
Assignee:
Altera Corporation
Inventors:
Yaron Kretchmer, Paul Leventis, Vaughn Betz
Abstract: Heat is extracted from compressed gas used in a blow-molding process by expansion cooling the exhausted gas and/or passing the exhausted gas through a vortex tube, which supplies cold gas at an exit thereof. The cold gas is then routed through cooling channels in the mold. This obviates the need for recirculating or externally chilling a coolant and saves energy.
Abstract: Multiple channel iontophoretic devices including multiple regulators, each of which are coupled to an associated electrode. A regulated current flows through each regulator in response to a control signal. The control signal is responsive to feedback indicative of current flowing through more than one of the multiple regulators.
Abstract: In a programmable logic device having high-speed serial interface channels, a clock distribution network for providing one or more high-speed clocks to dynamic phase alignment circuitry of those high-speed serial interfaces includes at least one bus that is segmentable (e.g. using tristatable buffers). This allows the bus to be divided into different portions that can be connected to different clock sources when the high-speed serial interfaces are running at different speeds. In one embodiment, the segmenting elements (e.g., the aforementioned buffers) are located between selected channels (e.g., every fourth channel), limiting the size of the different segments. In another embodiment, segmenting elements are located between each channel, allowing complete user freedom in selecting the sizes of the segments. Thus, instead of providing a bus for every clock source, multiple clocks can be made available to different channels by segmenting a single bus.
Type:
Grant
Filed:
November 25, 2009
Date of Patent:
December 28, 2010
Assignee:
Altera Corporation
Inventors:
Gregory Starr, Kang Wei Lai, Richard Y. Chang
Abstract: Method and circuitry for implementing high speed multiple-data-rate interface architectures for programmable logic devices. The invention partitions I/O pins and their corresponding registers into independent multiple-data rate I/O modules each having at least one pin dedicated to the strobe signal DQS and others to DQ data signals. The modular architecture facilitates pin migration from one generation of PLDs to the next larger generation.
Type:
Grant
Filed:
December 6, 2008
Date of Patent:
December 28, 2010
Assignee:
Altera Corporation
Inventors:
Philip Pan, Chiakang Sung, Joseph Huang, Yan Chong, Bonnie I. Wang
Abstract: A video recorder, adapted for use in conjunction with a remotely controllable unit associated with television recording and/or viewing, contains a remote-control signal transmitter to transmit control codes to the associated unit, and means to analyze the operation of the associated unit in response to the control codes. An electronic controller causes the transmitter to transmit test codes to the associated unit, then analyzes the resulting operation of the associated unit to determine its control codes, which it stores in a memory for later use.