Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit. In an implementation, the programmable phase shift circuitry is implemented using two programmable counters.

Abstract: A mask-programmable logic device includes some circuitry that is electrically programmable as in conventional programmable logic devices. This allows a user to adjust certain characteristics of programmed devices whose logic functions have been proven and need not change, but which operate in an environment that changes, necessitating different characteristics, without having to redesign the programming metallization layers, and therefore without involving the device manufacturer. The programmable elements may include input/output elements, which may need adjustment because the signal characteristics of the larger system change, or clock circuitry, which may need adjustment because environmental conditions such as changes in the expected operating temperature may affect clock signals in the larger system.

Abstract: A porous ?-tricalcium phosphate material for bone implantation is provided. The multiple pores in the porous TCP body are separate discrete voids and are not interconnected. The pore size diameter is in the range of 20-500 ?m, preferably 50-125 ?m. The porous ?-TCP material provides a carrier matrix for bioactive agents and can form a moldable putty composition upon the addition of a binder. Preferably, the bioactive agent is encapsulated in a biodegradable agent. The invention provides a kit and an implant device comprising the porous ?-TCP, and a bioactive agent and a binder. The invention also provides an implantable prosthetic device comprising a prosthetic implant having a surface region, a porous ?-TCP material disposed on the surface region and optionally comprising at least a bioactive agent or a binder. Methods of producing the porous ?-TCP material and inducing bone formation are also provided.

Abstract: The present invention relates to novel classes of compounds which are caspase inhibitors, in particular interleukin-1? converting enzyme (“ICE”) inhibitors. This invention also relates to pharmaceutical compositions comprising these compounds. The compounds and pharmaceutical compositions of this invention are particularly well suited for inhibiting caspase activity and consequently, may be advantageously used as agents against interleukin-1-(“IL-1”), apoptosis-, interferon-? inducing factor-(IGIF), or interferon-?-(“IFN-?”) mediated diseases, including inflammatory diseases, autoimmune diseases, destructive bone disorders, proliferative disorders, infectious diseases, and degenerative diseases. This invention also relates to methods for inhibiting caspase activity and decreasing IGIF production and IFN-? production and methods for treating interleukin-1, apoptosis-, and interferon-?-mediated diseases using the compounds and compositions of this invention.

Abstract: A programmable logic device (“PLD”) architecture and a user logic design are modeled logically to find an efficient programming solution for the user logic design on the PLD architecture. The logical models are converted to equations—e.g., by representing them as binary decision diagrams which can be modeled and manipulated mathematically with commercially available tools. The equations can be solved for the programming or configuration variables. Similarly, an efficient programmable logic device architecture for implementing one or more of a given set of logic functions can be found by mapping each function in the set of functions onto a generic architecture and solving for the configuration variables. By comparing the results for all functions, one can reduce the generic architecture to an efficient architecture for that set of functions by eliminating structures from the generic architecture whose configuration bits are the same for all solutions.

Abstract: An FPGA equivalent of a structured ASIC implementation of a user's logic design is produced by taking advantage of various aspects of the way in which the structured ASIC implementation was produced. For example, the structured ASIC breaks the user's logic design down into blocks that are readily implemented in basic units of the FPGA circuitry. Starting from such an acceptable ASIC mapping of the user's logic, resynthesis for FPGA implementation can be performed, at least as a first step, on a block-by-block basis. The FPGA implementation can then be made more economical and efficient by looking for blocks that can be combined in individual basic units of the FPGA circuitry.

Abstract: Systems and methods for locating the shooter of supersonic projectiles are described. The system uses at least five, preferably seven, spaced acoustic sensors. Sensor signals are detected for shockwaves and muzzle blast, wherein muzzle blast detection can be either incomplete coming from less than 4 sensor channels, or inconclusive due to lack of signal strength. Shooter range can be determined by an iterative computation and/or a genetic algorithm by minimizing a cost function that includes timing information from both shockwave and muzzle signal channels. Disambiguation is significantly improved over shockwave-only measurements.

Abstract: Disclosed herein are systems, methods and apparatus, for detection and identification of analytes in a volatilized or volatilizable sample, using the mobility-based signature that is produced when the volatilized sample is passed through an ion mobility based analyzer.

Abstract: A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

Abstract: A method, apparatus, and article of manufacture for reducing broadcast traffic in a wireless backbone network. In operation, a wireless access point receives an address resolution protocol (ARP) message from a network device. The wireless access point determines the destination of the ARP message and attempts to identify the Ethernet address associated with the destination network device. If the Ethernet address cannot be determined, the access point sends an ARP request message to the other wireless access points on the network, requesting them to transmit ARP packets to the network device. When the desired network device comes within range of the network, the access points discontinue transmitting ARP packets and a message acknowledging the device's presence is transmitted to the original access point. This method of having access points periodically broadcast ARP packets to network devices reduces ARP broadcasting across the wireless backbone, thereby increasing network throughput.

Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

Abstract: Clock data recovery (CDR) circuitry can be provided with dynamic support for changing data rates caused by the interfacing of different protocols. The CDR circuitry, which operates in reference clock mode and data mode, can be controlled by two control signals that signal the CDR circuitry to automatically switch between reference clock mode and data mode, to operate only in reference clock mode, or to operate only in data mode. The control signals can be set by a programmable logic device (PLD), by circuitry external to the PLD, or by user input. A dynamically adjustable parts per million (PPM) detector can also be provided in the CDR circuitry to signal when processing of data during the reference clock mode is completed.

Abstract: Systems and methods for providing fast and efficient data compression using a combination of content independent data compression and content dependent data compression. In one aspect, a method for compressing data comprises the steps of: analyzing a data block of an input data stream to identify a data type of the data block, the input data stream comprising a plurality of disparate data types; performing content dependent data compression on the data block, if the data type of the data block is identified; performing content independent data compression on the data block, if the data type of the data block is not identified.

Abstract: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.

Abstract: A portable ultrasound unit and docking cart for the unit are provided. When the portable unit is mounted to the docking cart, the docking cart transforms the portable unit into a cart-based system with enhanced features and functionality such as improved ergonomics, ease of use, a larger display format, external communications connectivity, multiple transducer connections, and increased data processing capabilities. A clinician display and patient display may be provided on the cart. Communications circuitry in the docking cart may be used to support communications between the docking cart's processor and external networks and devices. The docking cart may receive physiological signals such as cardiac signals and may use this information to synchronize ultrasound imaging operations with a patient's physiological condition. Adjustable user interface controls, data handling features, security features, power control functions, and thermal management capabilities may be provided in the docking cart.

Abstract: This invention relates to methods for the stabilization, storage and delivery of biologically active macromolecules, such as proteins, peptides and nucleic acids. In particular, this invention relates to protein or nucleic acid crystals, formulations and compositions comprising them. Methods are provided for the crystallization of proteins and nucleic acids and for the preparation of stabilized protein or nucleic acid crystals for use in dry or slurry formulations. The present invention is further directed to encapsulating proteins, glycoproteins, enzymes, antibodies, hormones and peptide crystals or crystal formulations into compositions for biological delivery to humans and animals. According to this invention, protein crystals or crystal formulations are encapsulated within a matrix comprising a polymeric carrier to form a composition.

Abstract: In general, the invention features methods and uses for transposon-mediated gene targeting which greatly enhance the insertion and detection of desired genes in genomic exons by homologous recombination. The invention also features transgenic non-human mammals, and eukaryotic cells, wherein a gene encoding 7B2 protein is modified, as well as nucleic acid vectors capable of undergoing homologous recombination with an endogenous 7B2 gene in a cell. The invention also features transgenic non-human mammals as models of endocrine disorders, as well as methods for diagnosing and treating patients with endocrine disorders.

Abstract: A book that is capable of displaying one or more coins related to its theme, including a front cover and a back cover. At least one book cover defines one or more apertures that are capable of receiving coins. The book theme is displayed on at least one of the book covers. The book may optionally include one or more caps that may be inserted into and removed from the coin-receivable apertures. These caps will preferably display images that are related to the theme of the book. The invention provides a coin specific display that stores and displays one or more coins in an appealing manner, and that also conveys or provides additional information about the theme displayed on the coin.

Abstract: Programmable logic circuitry includes level-sensitive latches as at least some of the data storage elements. At least some of the latches are enabled by one phase of a clock signal, and at least some others of the latches are enabled by the other phase of the clock signal. Accordingly, these latches collectively have two-phase operation. These two-phase latches may replace at least some single-phase, edge-triggered flip-flops in a user's logic design, and may thereby increase the speed at which the user's logic can be operated. Methods for converting a single-phase, edge-triggered flip-flop design to a logically equivalent design using at least some two-phase latches are disclosed.