Abstract: There is disclosed a sample selection and data alignment circuit that is able to recover (retime) a data on a predefined phase of a multiphase clock signal. A plurality of over sampled signals (G0, . . . , Gn?1) is obtained by over sampling an incoming serial binary data (bits) stream with the n phases (G0, . . . , Gn?1) of a multiphase clock signal. A reliable over sampled signal is selected according to a selected signal (G0, . . . , Gn?1) generated by an edge detector which designates which over sampled signal is the best for subsequent processing.