Abstract: An automatic gain control, AGC, circuit comprising with a preferred transition region. A gain correction unit is responsive to an attenuate command and amplify command coming from a feedback system monitoring the AGC's output. The feedback system can individually adjust the delays of both attenuate and amplify commands sent to the gain correction unit. Additionally, the present AGC also includes a transition region detector that monitors the input signal applied to the AGC to from a feedforward system. The transition region detector producing a control output to selectively permit the gain correction unit to respond to an attenuate or amplify command. If the magnitude of the input signal is greater than a predetermined value, then it will place a disable signal on its control output to prevent the gain correction unit from altering its gain.

Abstract: A microcontroller having a special function register to internally select between internal memory and external memory on the fly. Two data pointers in conjunction with the special function register result in four effective quick reference locations. The internal memory consists of one memory module having its array subdivided into a data memory store and a code memory store, and having a bank of pass devices to selectively isolate the code memory store from the data memory store. The present memory can further support concurrent writing to the data memory store while reading from the code memory store. This is done through one of two memory embodiments. In a first memory embodiment two y-decoders are used; a first y-decoder adjacent the code memory store and a second y-decoder adjacent the data memory store. When a simultaneous read/write instruction is started, the outputs from the second y-decoder and an x-decoder are latched.

Abstract: An oscillator circuit having a first node oscillating with a first indeterminate duty cycle and having a second node oscillating with a predetermined second duty cycle. Both nodes oscillate at similar frequencies. A variable current source and a switch are coupled in series between Vcc and ground with the output of the variable current source being the second node. The first node controls the switch, which is closed when the first node is at a first logic state and is opened when it is at a second logic state. During each cycle, a monitoring circuit measures the time span that the first node is at the first logic state and adjusts the magnitude of the variable current source to make it directly proportional to the measured time span. By adjusting the variable current source, the second node can be made to reach a desired voltage level in a desired amount of time during each cycle. In a second embodiment, a current limiting transistor is inserted between the second node and the switch.

Abstract: The present invention discloses an integrated constant bias voltage generator using only active devise to simulate a high impedance node, as seen from a capacitively coupled input signal. A reference current source an MOS device are coupled in series between Vcc and ground with the drain electrode of the MOS device being the constant bias voltage output. An input signal capacitively coupled to said drain electrode introduces an error current monitored by a current monitoring means. A feedback means responsive to the current monitoring means modulates the control input of the MOS device to select a IDS vs. VDS characteristic curve which will maintain the VDS voltage constant for any given IDS current, including the error current. The feedback means also compensates for voltage fluctuations in Vcc.

Abstract: A clock distribution apparatus with active phase alignment which makes the incidence of a timing event occur essentially simultaneously at multiple physically remote destinations. The circuit uses traces configured as reflective transmission lines with a matched impedance input. The propagation time of a transmission line is determined by monitoring the current into the transmission line. Variable delays are determined for each transmission line by measuring the actual propagation time and reducing a predetermined maximum delay time by that amount. The variable delay values are stored and used to retard clock edges by the varying amounts so that all clock edges arrive at respective remote destinations at a time equal to the maximum delay time.

Abstract: A fully integrated voltage-to-current converter consisting of a two-stage direct amplifier with an overall feedback network having an active differential current-to-voltage converter. The first stage of the two-stage direct amplifier is a voltage-to-voltage converter receiving an input voltage signal, and the second stage is a transconductance amplifier supplying an output current. In the overall feedback network, a voltage measure of the output current is applied to a differential amplifier which cancels out all DC components and amplifies only the AC components. The amplified AC components are fed back to the input. The feedforward gain of the two-stage direct amplifier and the feedback gain of the overall feedback network may be separately adjusted. The differential amplifier includes a local resistive feedback network such that the local gain of the differential amplifier is determined by resistor values and does not introduce any non-linear elements.

Abstract: A current cell for switch current circuits includes first and second MOS transistors connected in series between a constant current source and a reference ground. The first MOS transistor has its drain coupled to the constant current source and the second MOS transistor has its source coupled to the reference ground. Each of the two MOS transistors has a respective first and second switch coupling its control gate to its drain. The sample phase of a sample and hold operation is broken down into a first and second sample sub-phase, and an input current is applied to the current cell during both sample sub-phases. During the first sample sub-phase, the second MOS transistor memorizes a gate voltage corresponding to the input current, constant current source current and a clock feedthrough error. A channel effect is purposely induced in the second MOS transistor to a degree sufficient to compensate for, and correct, its clock feedthrough error.

Abstract: An SRAM configures its bitline load structure to implement one of three different precharge schemes, none of which use an ATD circuit. The SRAM monitors its WRITE/READ pin and initiates a first precharging scheme when the SRAM is in a read mode. In the first precharging scheme, every complementary bitline pair is directly coupled to Vcc via a first pmos transistor which is permanently turned on, regardless of whether a memory cell is being read or not. Additionally, both true and false bitlines in every complementary bitline pair are coupled together via a pmos transistor as long as the SRAM remains in a read mode. When in a write mode, the second precharging scheme is initiated causing the second pmos transistor to be turned off and only the first pmos transistors remain active. Thus, all complementary bitline pairs which are not selected for a write operation are pulled up to Vcc by the first pmos transistors.

Abstract: A sector programmable EEPROM memory capable of emulating the byte programmable functionality of full-featured byte programmable EEPROMs. The EEPROM memory incorporates an on-chip write cache used as a buffer between byte level data entered by the user system and word level data written to the main memory core. The EEPROM main memory core is divided into memory pages with each memory page further divided into sub-page sectors, and each sub-page sector holding a multitude of multi-byte data words. The sub-page sectors within a memory page can be individually or collectively subjected to a program and erase cycle. The EEPROM memory incorporates an ECC unit used to recover and refresh lost data in the memory core. The EEPROM memory is also capable of interruptible load cycles.