Abstract: A redundant (multiple) bus system for interconnecting a plurality of data source and destination entities and arranged to direct data communications over an alternative bus in the event that a prior call to a destination over a first bus was unsuccessful. Each source entity maintains a table designating a separate logical path over each bus to each destination entity, marking each path designation in accordance with the success or failure of calls directed through the path. The bus selection for delivering a communication to any destination is determined in accordance with designation markings for the paths to the destination and independent of designation markings for paths to other destinations whereby a bus may be selected for a delivery to one destination even though prior deliveries over the bus to other destinations have failed.

Abstract: A multi-stage time division switch interconnects a plurality of processors that individually communicate over one or more channels at various signalling rates. Any processor may initiate a call and request that a connection be set by the switch. The switch assigns one or more time slots to the call and gathers or distributes data over the interconnecting channels through the utilization of polling techniques, thereby creating a virtual circuit through the combination of a time division switch and a polled communication line.

Abstract: A multi-stage time division switch interconnects processors communicating over one or more channels on time division lines. One of the processors is designated as a common processor to provide the switching "mapping" information for the various stages of the switch sending the switching information to the memory and logic of each switched stage over dedicated channels which include channels on the time division line emanating from the common processor and time division channels which pass through several switches until the memory of the applicable switch is accessed.

Abstract: A geographically distributed multiprocessor system is implemented by locating groups of processors at nodes which are interconnected by way of a transport network and which are connected by way of local lines to customer terminals and hosts. Each processor supports a plurality of processes including certain process executing programs "customized" for the customers and other processes executing programs having "universal capabilities" which serve common needs of a plurality of customers. Processes communicate with other processes in the same processor by way of internal links and with other processes in other processors by way of combinations of internal links and external communication links. Interface processes exchange data between the internal and external links.

Abstract: A geographically distributed multiprocessor system is implemented by locating groups of processors at nodes which are interconnected by way of a transport network and which are connected by way of local lines to customer terminals and hosts. Each processor supports a plurality of processes which communicate with other processes in the same processor by way of internal links and with other processes in other processors by way of combinations of internal links and external communication links. Interface processes exchange data between the internal and external links. A process can initiate a call to any other process and define the communication parameters for exchanging data information by selecting the appropriate internal link and supplying the code defining the communication parameters to the selected internal link.

Abstract: Flow of data packets through virtual circuits in a multinode packet switching network is controlled by authorizing packets to enter and to leave each node. When a packet entering a node does not have an authorization (credit) to leave, it is placed in a pool of buffers common to all virtual circuits to await reception of an output credit for the virtual circuit. To avoid buffer congestion, a count is maintained of packets presently stored in and being processed through the node and packets that the node anticipates it will receive. If the count exceeds a predetermined threshold, a packet cannot get an authorization to enter the node unless it has a credit to leave. If the count is below the threshold, credits are granted for packets to enter the node even though there is no authorization to leave.

Abstract: A technique for ensuring independence of random samples of input queues of time-shared processing systems taken during a fixed interval to determine system usage involves interposing guardband intervals of minimum time duration between such samples. A stratified sampling method is disclosed which develops successive stratum or subintervals, positions a data sampling at a random point in each subinterval and interposes a guardband interval between successive subintervals. A simple random sampling method is disclosed which takes a sampling at the termination of a random subinterval and interposes a guardband interval between successive random subintervals.

Abstract: Apparatus for testing multi-conductor cables for wiring errors, illustratively open, shorted or crossed conductors, is described. This apparatus, at the so-called far end of the cable, establishes a conduction path between all of the conductors, and, at the so-called near end, sequentially selects one of n-1 of the n conductors comprising the multi-conductor cable and establishes a conduction path between it and the n.sup.th conductor. As a result, a test loop is defined which at any one instant is comprised of only two conductors: the selected conductor and the n.sup.th conductor, wherein the latter serves as a fixed return path. At the near end, the apparatus applies a pulse of test current to each test loop in succession which, if the selected conductor comprising that loop is correctly wired, flashes a corresponding indicator located in the apparatus at the far end.

Abstract: Various size frames or pages of information elements stored in a computer system can be simultaneously displayed on a screen-based terminal. The computer processor identifies the screen position the user selects for each of the stored pages and the top-to-bottom order of the pages with respect to visibility in the event that pages overlap. The processor selects the pages in descending order, topmost page first. Information elements of selected pages are transferred to appropriate locations in a display memory only in the event that an auxiliary memory registers that an information element has not priorly been transferred to those locations. After all the pages are transferred, background data is written into each display memory location that the auxiliary memory registers as not having an information element transferred thereto. The display memory is scanned in a conventional manner to apply the display information therein to the viewing screen.

Abstract: In a delta modulation coder and decoder system, the disadvantageous effects of slope overload are eliminated by reversing the polarity of the feedback signal in the coder and the polarity of the reconstructed analog signal in the decoder whenever slope overload correction is required. This is accomplished by the addition, to both the coder and decoder, of control circuitry which determines whether slope overload correction is required. To make the determination, first the digital output signal of the coder is tested to determine whether its rate of change is equal to a maximum value. Second, the magnitude of the feedback signal is tested to see if it lies below a threshold value. If both these conditions are satisfied, slope overload correction is then performed.

Abstract: The phase of timing signals is compared with the phase of incoming digital signals to produce phase error signals and repeated phase corrections of the timing signals are made in accordance with the phase error signals. The phase corrections are initially delayed until phase error signals exceeding a predetermined magnitude persist for a predetermined interval of time. The corrections are removed without delay when the phase error signals are discontinued.

Abstract: An improved ringing control circuit in a stored program telephone switching system which provides a called subscriber an interval or window of time after answering a call to send a request for special services such as identification of the number of the calling party. This time interval, initiated when ringing is tripped, delays operation of current sensitive devices which sense current flow in the subscriber line when the party answers the call. This delays completion of the connection by the systems processor which periodically scans the conditions of the current sensitive devices. A detecting device is also provided in the control circuit to detect receipt of the request for service signal during the time interval.

Abstract: A subscriber at a remote location is provided the capability of configuring a multipoint private line network composed of multipoint junction units or hubs that provide alternative functions of permitting exclusive data intercommunication between main lines thereof and selected branch lines thereof when certain selection codes are applied to the main lines without the subscriber having knowledge of the selection codes or the network "mapping". The subscriber at the remote location sends a service request defining the function desired and the ultimate downstream terminal to be interconnected or blocked and a control unit in the network consults a network map to identify the upstream and downstream branch lines to be selected, sending a sequence of selection codes to first select the upstream branch and then select the downstream branch or branches. The control unit also monitors responses of the junction units and reports results to the control location.

Abstract: A central controller (104) for a multipoint polling system arranged to collect inquiry messages from data terminals (102a-n, 103a-n) for processing by a data base (101) and for distributing response messages to the terminals, the several terminals using different communication protocols. The controller includes a RAM memory (203) which stores a list of items, each item identifying a terminal and the type of protocol used thereby, a ROM memory (202) which stores an instruction set for each protocol type and a microprocessor (201) which sequentially accesses each item on the list to poll the associated terminal and accesses the instruction set identified in the item to control sending and receiving equipment to query and intercommunicate with the selected terminal in accordance with the accessed instructions.

Abstract: Recovery of eight-bit data characters imbedded in the time slots of a train of data bytes individually having six slots available is implemented by a process which locates the bit alignment of a first one of the characters and executes a sequence of assembly procedures to appropriately form this and subsequent characters. The data characters are available as bursts of data characters preceded by synchronizing words having a predetermined bit sequence to create data blocks, the sequential bits of the block being inserted in sequential available slots of the byte train. Recovery is accomplished by comparing the bits of each byte with stored patterns corresponding to overlapping portions of the synchronizing word. A comparison match identifies the bit location of the first character in the burst to thereby define one of a plurality of assembly procedures which process the bits in the identified locations to form the character.

Abstract: Communication between a plurality of data stations (100(1)-100(N)) serially interconnected by way of a line (101) arranged in a ring is provided by bit interleaved data packets. A control station generates framing signals to designate the start of each packet, staggering the packets so that only one packet header appears on the line at a time. Processing equipment (114) at each station monitors all the headers, seizing "empty" packets if the station has a data burst to send and reading the data burst if the packet is addressed thereto.

Abstract: Communication between a plurality of data terminals (101(1) to 101(b)) serially interconnected with a main terminal (102) is provided by data frames or packets having a data portion for accommodating a burst of data preceeded by a header portion for accommodating address data followed by an empty/full "flag" bit indicating whether the addressee station has withdrawn the data burst. If a terminal has a data burst to send, it locates an empty packet, inserts the addressee designation in the packet subsequent to any prior address that the packet might contain, interposes delay in the passage therethrough of the packet so that the duration is increased to accommodate the new address and overwrites the data burst into the data portion. The main terminal detects when the data burst is withdrawn and signals the originating terminal to remove the data delay.

Abstract: The peak output of a commutating capacitor triplet device (201) which contains three capacitors (10, 11, 12) connected in pairs across an input signal to provide six samples of each signal cycle, is obtained to provide envelope detection. To reduce output ripple by increasing the number of samplings of each cycle without increasing the number of capacitors, a portion of the output is obtained at the junction (13) of the capacitors, the amplitudes of the output and portion thereof are weighted with respect to each other by resistors (204, 205) and combined. In one embodiment, the positive and negative parts of the combined signal are applied to a full wave rectifier (207, 208, 214). In another embodiment, the positive and negative parts of the portion are inversely combined (306, 307, 308) prior to the portion being combined with the output of the triplet device.

Abstract: The information in the header portion of a data packet, which header includes the old module and channel numbers, is used to access locations in a random access memory which contain new module and channel numbers or words that identify the packet routing. To convert the "virtual" address defined by the old module and channel numbers to a physical address, the module number accesses a memory word which is combined with the channel number to produce a single physical address number. When the information stored in the memory is to be changed, the header has special module and channel numbers and the following data includes a "write" command word, address data and information data. The special header words access a memory word which enables the writing of the information data into memory locations selected by the address data. A "read" command word in the packet inserts the word accessed by the address data into the packet.

Abstract: A digital data transmission system comprising a plurality of interconnected switching units, each such unit having connected thereto at least one transmission loop, and each such loop having at least one digital device attached thereto. The system provides controllable buffering of digital data thereby allowing digital devices having different data transfer speeds and storage capabilities to communicate asynchronously. The system allocates communication resources upon request but only creates actual communication paths when the requesting device is transmitting data. Thus system resources need not remain committed between bursts of data.