Abstract: A large, fault tolerant, highly reliable semiconductor data storage system (memory) is designed to have the memory function striped across multiple symbol planes which comprise individual fault containment regions. Each fault containment region includes such a symbol plane which, in turn, stores at least one bit of any given memory word accessed in the system. The system further includes a processing core module, including at least symbol plane addressing controls, and a channel adapter is provided for selectively connecting the memory to high speed communications channels for, in turn, communicating with client processors or other functional entities attached to the data store system. The processing core contains an error correction/detection mechanism for the error checking and correction of all data fetched from the memory and for generating error correction and detection code bits for all data to be stored in memory.

Abstract: A solid state microwave generator is utilized as an excitation source for material/ plasma processes. The invention provides very close precise control of the solid state device's power levels to control the ultimate power output and frequency which control is not readily possible with vacuum tube devices. Utilizing the concepts of the invention the total power generated by the system may be easily varied and, further, the power may be easily monitored and used to control other device parameters such as frequency and the like. Because of the degree of control possible within the overall process system of the invention any measurable physical property of the process such as temperature, power, color (e.g., optical pyrometer), or the like that can be monitored and converted to a control signal can be utilized by the present system to carefully control the overall process conditions. These control features are lacking in currently available vacuum tube microwave devices.

Abstract: An electronic computer system including a central processor and a hierarchical memory system having a large relatively low speed random access system memory and a small high speed set-associative cache memory including a data store section for storing lines of data from the system memory and a cache directory for indicating, by means of line identifier fields at any time, the lines of the system memory data currently resident in cache, is provided with a way to improve the distribution of data across the congruence classes within the cache. A mechanism is provided for performing a permutation operation on an M bit portion (X) of the system memory address, which permutation determines the congruence class into which the address will map. The permutation mechanism performs a bit-matrix multiplication of said M-bit address with an M.times.M matrix (where M is a real positive integer greater than 1) to produce a permuted M-bit address (X').

Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor.

Abstract: An aperiodic mapping procedure for the mapping of logical to physical addresses is defined as a permutation function for generating optimized stride accesses in an interleaved multiple device system such as a large, parallel processing shared memory system wherein the function comprises a bit-matrix multiplication of a presented first (logical) address with a predetermined matrix to produce a second (physical) address. The permutation function maps the address from a first to a second address space for improved memory performance in such an interleaved memory system. Assuming that the memory has n logical address bits and 2.sub.d separately accessible memory devices (where d.ltoreq.n) and a second address that utilizes n-d bits of the first address as the offset within the referenced device node. The procedure includes performing a bit matrix multiplication between successive roows of the said matrix and bits of the first address to produce successive d bits of the second address.

Abstract: A method for compressing an LR, LALR, or SLR parsing table into a compact and time-efficient representation which is machine and language independent, and allows access to table entries with a constant number of primitive operations. The primitive operations used: addition, comparison, and vector indexing, are in general very efficiently implemented on most machines, and are the key to the superior time performance of this method over other methods. Transformations are applied to the parsing table prior to compression.

Abstract: A cursor control/data input device for a computer display system which utilizes a conventional X-Y mouse provided with a third Z with axis data generating mechanism. The mouse may be used with any non-specific support surface and would have conventional X-Y data generating wheels or a rotating ball with appropriate pick-up elements to generate the X-Y coordinate data. Third, or Z, coordinate data is produced by a third instrumentality in the mouse body, preferably operable by the operator's thumb or index finger. Means comprising a pressure sensitive button mounted on the surface of the mouse, or alternatively means actuated by the insertion of the operator's finger into a hole provided in the mouse's body, generate said Z coordinate data. Movement of the finger in the hole is measurable by any of a number of different instrumentalities.

Abstract: A stylus and table X-Y data input system for a video display system. The pen includes an optical styling having a suitable pickup mechanism and the tablet is passive in nature and provides direct digitized data readout. Absolute positional information is encoded in binary form in the tablet in such a fashion that the pen position upon the tablet is automatically determinable by illuminating a particular area of the tablet and reading off the digitized X-Y coordinate data stored therein. The pen and supporting hardware/software are rotationally insensitive so that the pen may be held in any desired position comfortable to a user. The system provides greatly improved resolution, sampling rate accuracy and general robustness particularly for such applications as text recognition as well as a wide variety of other graphical input uses.

Abstract: An interconnection network management architecture for use with a large shared memory multiprocessor computing system including a plurality of processors and a plurality of separately addressable main memory modules. Two parallel, interconnection networks are provided each capable of interconnecting any processor to any memory module, and each having different latency characteristics. A Hot-Spot detection mechnaism is associated with each main memory module for detecting when a particular address in that module has become a Hot Spot and includes a first memory for storing all detected Hot Spots. A diverter element is associated with each processor for selectively routing memory requests over either the first or second memory network contingent on its status as a Hot Spot. A second memory is included in each diverter element for storing all Hot Spots detected by the detector elements.

Abstract: A mouse for use in a video display system for controlling cursor movement on a display screen provided with feedback means which produces resistance to the motion of the mouse as the cursor moves across predetermined areas of the display screen. In its most straight forward realization it comprises an electromagnet and control circuit which operates independently of the pickup and location sensing control of the mouse to produce a magnetic field which acts cooperatively with a substantially planar magnetic surface to produce a resistance to the motion of the mouse when energized.

Abstract: A data processing system is provided which includes ALU data busses, temporary operand storage registers, an accumulator, and a set of latches for temporarily storing data to be supplied to the input of the ALU. Output multiplexer is provided which can select the output of one of the latches or that of the ALU which is sent to the accumulator. A detector is also provided for determining whether the smaller or larger one of two data elements is stored in said latches according to the status of the ALU and a new MIN/MAX instruction and the selected data element is returned to a predetermined temporary storage register via the output multiplexer. A controller operates in cooperation with the system instruction decoder to effect this operation with a single machine instruction.

Abstract: A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.

Abstract: A method for improving the quality of code generated by a compiler or assembler, for a target machine that has short and long forms of some of its instructions with the short forms executing faster or occupying less space. The method first determines which bits of the result of each computational instruction are significant, by a backwards pass over the program that is similar to liveness analysis. Then the significant bits thus computed are used to guide the code selection process to select the most efficient instruction that computes the correct result in all the significant bit positions.

Abstract: A method for increasing the wirability of complementary metal oxide semiconductor (CMOS) differential cascode voltage switch (DCVS) logic circuits which comprises designing the circuitry to permit as many of the internal tree connections as possible to be wired using diffusion techniques. The method utilizes differential pair and load microblocks which have been designed so as to allow mirroring on a vertical center line. Utilizing the availability of mirroring for individual pairs plus relocation of individual pairs in the logic tree the crossings may be largely eliminated in a shortened period. It utilizes a step by step row and column analysis of the initial or starting tree design resulting from the basic Boolean logic to be performed by the particular circuit and makes required load mirroring and differential pair relocation decisions in an iterative process. The transistor pairs and load devices may be mirrored about a vertical center line.

Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement within the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory.The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Modification of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted.

Abstract: The inspection of the walls of a deep hole of minute diameter in a structure such as an integrated circuit board is carried out by inserting into the hole a reflective optical sphere having a diameter at least slightly smaller than the hole diameter. A coated optical fiber having a diameter substantially less than the diameter of the sphere has one end attached to the sphere. An optical scattering means is interposed between the sphere and the fiber to disperse illumination from the optic fiber to illuminate the walls of the hole. A source of illumination is provided at the opposite end of the optic fiber, and an optical system is positioned axially at the end of the hole to pick up the image of the illuminated walls reflected from the sphere.

Abstract: The programmable logic controller uses a set of instructions which comprises only three instructions: a Read instruction and a Write instruction which includes an operation code, a condition bit, and an address, and a Jump instruction which includes an operation code and an address. When a Read instruction is read from control memory (10), a condition latch (35) is set to 1 or 0 depending on whether the level of the addressed input corresponds or not to the level of the condition bit. For a Write operation, the state of latch (35) or its inverse is provided at the addressed output in accordance with the value of the condition bit. A Jump instruction is executed only if the condition latch (35) is set to 1. A random access memory (50) may be utilized to function as one of the input multiplexers (RI0 to RI2) and one of the output demultiplexers (RO0 to RO2), which allows the controller to store events and to use said events later on.

Abstract: A method for improving the quality of code generated by a compiler in terms of execution time, object code space, or both. The method is applicable to computers that have a redundancy of instructions, in that the same operation exists in forms that operate between registers, between main storage locations, and between registers and main storage. The method selects the best form of each such instruction to use, for the context in which the instruction lies.

Abstract: A method for use during the optimizatin phase of an optimizing compiler for performing global common subexpression elimination and code motion which comprises:Determining the code `basis` for the object program which includes examining each basic block of code and determining the `basis` items on which each computation depends wherein `basis` items are defined as operands which are referenced in a basic block before being computed. The method next determines the "kill set" for each `basis` item. Following this UEX, DEX, and THRU are determined for each basic block using the previously determined `basis` and "kill set" information. AVAIL and INSERT are computed from UEX, DEX, and THRU, and appropriate code insertions are made at those locations indicated by the preceding step, and finally redundant code is removed using the AVAIL set.

Abstract: An electrochromic matrix display of the kind in which the display electrodes are supported on a substrate above a corresponding matrix of transistor switches employs constant current writing and potentiostatic erasure. The transistors are switchable by signals applied on respective gate lines to pass electric current on the respective drive lines to their display electrodes. Gate and drive selection means define the active gate and drive lines During erasure, the potentiostatic erase voltage is applied to both ends of the selected drive lines simultaneously to speed up the current limited asynchronous erase operation. Optionally, the display may be driven alternately from opposite ends of the drive lines during a line-by-line writing operation.