Abstract: A locking mechanism is incorporated in a high-resolution video display system including a monitor, a computer for providing controls signals to said display system and two frame buffers, one for storing computer generated graphics images and one for storing video data both of said buffers being operable under control of said computer for reading out data to the monitor. The locking mechanism includes an output lock functionally located between the output of both of the frame buffers and the monitor for preventing video data from overwriting graphics data on said monitor screen. An input lock is also provided for preventing static video data stored in predetermined regions of the video frame buffer from being continually overwritten by motion video data being continually supplied to the video frame buffer.

Abstract: A character recognition system and method using the generalized Hough transform are disclosed. A template table which stores edge point parameters to be used for the generalized Hough transform is compressed so as to include only predetermined parameters, and is then divided into a plurality of template tables which are respectively loaded in the memories of a plurality of subprocessors operating in parallel under the control of a main processor. In performing recognition processing, these subprocessors operate in parallel according to their related partial template tables. Character recognition using the generalized Hough transform provides a high rate of character recognition. Also, parallel processing using the compressed template tables and partial template tables helps shorten table search time and computation time, thereby increasing processing efficiency.

Abstract: An interface architecture for interconnecting a plurality of video display devices together over a high speed digital communication link having limited bandwidth provides at each node for transmitting during a "transmit mode"; (1) sequential pixels of digital data (COMVIDOUT) comprising separate luminance and chrominance fields, from a digital TV source associated with each display node which data represents a scaled video window, (2) the local system clock (SCLK), (3) vertical and horizontal communication sync signals (COMVSOUT and COMSHOUT), (4) luminance and chrominance clock enable signals (COMYOCE and COMCOCE) based on a scaling algorithm utilized in the transmitting video device to insure that both the proper pixels and the proper luminance and chrominance fields associated with these pixels are selected by the communications device for transmission.

Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture of the internal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units.

Abstract: A process for forming chromium dioxide thin films which are receptive to high density magnetic recording. The process comprises depositing both chromium and oxygen on a substrate by evaporative techniques and concurrently bombarding the substrate with high energy ions of at least one of the film constituents to form a latent CrO.sub.x film forming layer. The process is carried out at approximately room temperature.The as-grown latent film forming layer is subsequently heat treated by a rapid thermal anneal step which raises the temperature of the as-grown film to about 500.degree. C. The rapid thermal anneal step preferably comprises a series of at least five separte pulses over a 10-second time span. After the rapid thermal anneal, the sample is rapidly quenched to room temperature.

Abstract: An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access function which provides an architectural organization for allowing the chip to be used in (1) a fast, "late-select" operation which may be provided with any desired degree of set-associativity while achieving an effective one-cycle write operation, and (2) a cache reload function which provides a highly parallel store-back and reload operation to substantially reduce the reload time, particularly for a store-in cache organization.

Abstract: A method and apparatus for controlling access to its general purpose registers (GPRs) by a high end machine configuration including a plurality of execution units within a single CPU. The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the GPR sequentially or different GPR's concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed.A series of special purpose tags are associated with each GPR and execution unit. These tags are used together with control circuitry both within the GPR's, within the individual execution units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

Abstract: A frame buffer memory organization which is capable of accessing a pixel aligned M by N array of contiguous pixels on the screen from a frame buffer memory constructed of an M by N array of memory chips by driving a common address bus to all the memory chips, and by driving N RAS wires horizontally across the memory chip array and M CAS wires vertically down the memory chip array. The writing of individual pixels in this array is enabled by energizing the write enable pins to each memory chip directly.The data wires in the memory organization are tied together such that M horizontal pixels in a single row can be read or written simultaneously. Additionally, all M and N pixels may be written simultaneously if the data in all vertical columns is the same.The frame buffer includes a selectively energizable plane mask for disabling desired planes of accessed pixels.

Abstract: A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data.

Abstract: An etching/deposition system comprising a hollow cathode electron source in combination with a magnetron sputter deposition plasma device within a containment chamber, said hollow cathode being disposed to inject electrons into the magnetic field of the magnetron plasma device adjacent to the magnetron cathode surface to which a deposition source is affixed. Said system further includes means for initiating and maintaining a discharge plasma within the hollow cathode and for initiating and maintaining the magnetron plasma. The improvement of the invention comprises a workpiece to be coated, located in said chamber, spaced from said magnetron cathode surface which may be biased to attract particles emitted by said deposition source.

Abstract: A multichannel data path architecture which assists a host processor in communication with the frame buffer in order to increase the overall system performance. The architecture provides automatic frame buffer data path rearrangement depending on the pixel address and the host data interpretation. It utilizes a minimum of shift registers, accumulators and control circuitry to provide the requisite storage, reconfiguration and frame buffer access functions. The architecture extends bit-blt (bit block transfer) conventional operations in order to provide high quality "antialiased" text and graphics directly in the architecture without requiring the calculation of colors by the host processor. Finally, it assists the "burst" mode update of an arbitrary single plane of a frame buffer, which is especially important when high denisty chips are used for the frame buffer implemenation.

Abstract: A vector generator for us with an all-points-addressable frame buffer capable of the non-word aligned access, simultaneously, of a square M by N array of pixels providing fast vector drawing independently of vector slope and position in the whole screen area of an attached display monitor. The vector generator utilizes a triangular logic matrix together with a line drawing unit to generate M vector bits lying in an M by N square matrix of the screen of an attached monitor in one memory cycle of the frame buffer and uses the generated matrix to generate a direct mask for the frame buffer whereby the M bit vector may be stored in a single memory cycle.

Abstract: A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law of addition. To achieve this, the requisite optimization of an object program or program segment, the following discrete steps must be performed after the strongly connected regions, USE and DEF chains have all been identified:1. Find the region constants and induction variables;2. Identify all of the essential computations;3. Write every essential computation as a sum of products;4. Exploit the use and DEF functions to substitute the definition of each operand R in an essential computation, if there is a unique computation of R in the strongly connected region and the defining operation is +, -, .times., or copy;5. Fix displacements;6.

Abstract: A branch target table (10) is used as an instruction memory which is referenced by the addresses of instructions which are targets of branches. The branch target table consists of a target address table (12), a next fetch address table (14), valid entries table (16) and an instruction table (18). Whenever a branch is taken, some of the bits in the untranslated part of the address of the target instruction, i.e. the instruction being branched to, are used to address a line of the branch target table (10). In parallel with address translation, all entries of the branch target table line are accessed, and the translated address is compared to the target address table (12) entry on that line.

Abstract: A display architecture is disclosed which supports a variable, selectable number of bits per chip and a variable, selectable segment width. The architecture comprises a plurality of dynamic memory chips and a function generator. Each of the memory chips includes at least two data islands wherein each data island has its own data in/out line, chip select and increment bit supplied by the function generator. The function generator receives a starting address X.sub.o, Y.sub.o, the data path width N.sub.D and an encoded segment width S. A bit incrementer in the function generator generates increment bits A.sub.I based on the externally supplied modulo N.sub.D. The function generator generates the physical word address w.sub.o and physical bit address b.sub.o based on the starting address X.sub.o, Y.sub.o, the data path width N.sub.D and the encoded segment width S. Logic circuitry is provided which is responsive to an overflow bit produced by the bit incrementer to control spill and wrap functions.

Abstract: A method of data compression which allows an enlarged font of complex characters to be produced by scaling from data representing a stored font of complex characters is disclosed. The scaling procedure involves the insertion of horizontal and vertical lines into the stored font to effect vertical and horizontal expansion, respectively, of the stored font. These lines are inserted so as to preserve the basic shape of the characters according to the following procedure. First, the dot matrix of each character is partitioned into sections, each containing a very pronounced and recognizable portion of the character. Then a decision is made in which sections to insert lines so that enlargement is attained without distorting the basic overall shape of the character. Next, a decision is made where in the sections the lines are to be inserted. Finally, a decision is made as to what the inserted lines are to look like.

Abstract: A compression technique for a character graphics system in which character cell definition bit strings are transmitted from a central processing unit to a display unit. Each cell is divided into a number of slices and each slice into digits. A test is made on whether to compress on a comparison with an all zero slice, the previous slice or the previous slice but one, depending upon the number of digit mismatches that occur when the comparison occurs. Slices are then compressed by comparing each digit with the corresponding digit in the comparison slice and generating a single 0 bit if the digit matches and including a 1 bit and the whole digit if a mismatch occurs. The compression in the central processing unit and the decompression in the display unit is implemented in microcoded routines.

Abstract: The present invention relates to a method and apparatus for compacting gray-scale image data which maintains extremely good picture quality and can result in typical images in a compression ratio of 5 to 1 and even better if a final step of arithmetic coding is used. The method is a special application of adaptive differential pulse code modulation (DPCM) which utilizes a prediction of smoothness surrounding a current pel to determine variable length codes to convey the quantized error. Thus, a continuously adaptive variable length code is produced which may be accurately decoded without using any further marker (code indicator) bits. For each pel and "error bit" is generated to indicate to the decoder if the predicted quantization range is adequate. These eroror bits can be further significantly compressed.

Abstract: A hybrid scheme for controlling transmission errors in digital data communication systems. Normally, data blocks with a small number of parity digits for error detection are transmitted. When the presence of errors is detected, the retransmissions are not the original data blocks but some properly selected blocks for correcting errors in those erroneously received data blocks which are stored in a buffer at the receiver. The retransmitted blocks are formed based on the original data blocks and error-correcting codes with an invertible property. When such blocks are received, they are used to recover the original data blocks either by an inversion operation or by a decoding process.

Abstract: This is a cipher system for enciphering a stream of binary data by means of a product cipher. A clear message represented in a binary data format is transformed into a cipher message by operating on each bit of clear information with a complex modulo-two addition function. This function is dependent on previous internal cipher digits transmitted and varies for each message bit processed. The function is developed by continually shifting a key matrix under the control of a varying control matrix. The control matrix is formed from the sub-product of the complex function developed in generating each cipher bit.