Abstract: A software platform in an Internet Protocol (IP) phone having the ability to be used with different communication infrastructures such as broadband, wireless communication and Plain Old Telephone System (POTS) service. Further, the software platform in the IP phone has the ability to be used with different applications operating on the IP phone. Further, the IP phone has the ability to perform additional functionality than traditional Public Switched Telephone Network (PSTN) phones, such as searches and advertising, given its ability to converge voice and data within a single terminal.

Abstract: The present disclosure provides a system and method accurately maintaining times and scoring for a sports activity.

Abstract: This device is noteworthy in that it comprises a band (3) made of a plastics material attached to the outer border or borders of the fabric (1), said band having at least one shaped molded tab (3a) integral with the band, said tab having the shape of a supporting cradle so as to be inserted against the opposing wall of the side member of the supporting structure, and in the intervals formed between said side member and a strip attached to said side member, and in that the area of the join between the band and the tab constitutes an area of resistance capable of taking the pressure of an undulating part of the strip, thereby enabling the tab to be locked in position relative to the opposing side member.

Abstract: This is a Braille display device which comprises: a plurality of cavities; and circuitry to individually excite the plurality of cavities. The plurality of cavities contain a positive and a negative electrode 18, 22, 26 and are filled with a quantity of polar organic gel 24 sensitive to electric fields. The cavities are sealed by an elastomeric film 14. The elastomeric film is held generally flat, by its own tension, in the absence of any voltage applied to the electrodes 18, 22, 26 in the plurality of cavities. The display device can also include circuitry to determine whether the cavity has been touched by person who is reading the display. The display device can also include circuitry to individually vibrate each cavity. Other devices, systems and methods are also disclosed.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector. The method may comprise: forming thermal isolation trenches 22 and contact vias 23 in a substrate 20; depositing a bias contact metal 32 into the vias 23 forming biasing contact areas around a periphery of the substrate 20; depositing a first trench filler 24 in the trenches 22 and vias 23; replanarizing; depositing a common electrode layer 25 over the thermal isolation trenches and the biasing contact areas; mechanically thinning the substrate 20 to expose the biasing contact area 32 and the trench filler 24; depositing a contact metal 34 on the backside of the substrate 20, the exposed trench filler 24 and the exposed bias contact area; and etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20. The thermal isolation trenches 22 and the bias contact vias 23 may be formed by ion milling or laser vaporization.

Abstract: This is an article of underclothing that may be worn under skirts and dresses. The article may comprise of: a plurality of rear panels 20, 22 attached together; a plurality of frontal panels 10, 12, 14 attached together and attached to the plurality of rear panels at two inseams and two outerseams 28 to provide a waist opening and two leg openings; and a frontal slip panel 24 attached to the plurality of rear panels 20, 22 and the plurality of front panels 10, 12, 14 at the two outerseams. The underclothing may include lace panels 26 attached to the leg openings to provide various lengths to the underclothing. The underclothing may also include a torso panels attached to the rear panels and the frontal panels to create a body suit with the underclothing. The underclothing may also include a cotton insert 16 attached to the frontal panels 10, 12, 14 and rear panels 20, 22 at a crotch area of the underclothing.

Abstract: A system for infrared sensing has thermally sensitive picture elements within a substrate; bias contact areas within the substrate and around a periphery of the thermally sensitive picture elements; a common electrode on a front side of the thermally sensitive picture elements and the bias contact areas; an optical coating on top of the common electrode; a first electrical contact metal on a backside of the thermally sensitive picture elements; and a second electrical contact metal connected to the bias contact areas on a backside of the bias contact areas and electrically connected to the common electrode. The bias contact areas may include a conductive substrate area. In addition, the device may be connected to an integrated circuit by an ohmic connection to the first and/or the second electrical contact metal.

Abstract: This is a system and method of forming an electrical contact to the optical coating of an infrared detector using conductive epoxy. The method may comprise: forming thermal isolation trenches 22 and bias contact vias 23 in a substrate 20; depositing a trench filler 24 in the thermal isolation trenches 22; depositing conductive epoxy 50 into the bias contact vias 23; replanarizing; depositing a common electrode layer 31 over the thermal isolation trenches 22 and vias 23; depositing an optical coating 26 above the common electrode layer 31; mechanically polishing a backside of the substrate 20 to expose the trench filler 24 and conductive epoxy 50; depositing a contact metal 34 on the backside of the substrate 20; etching the contact metal 34 and the trench filler 24 to form pixel mesas of the contact metal 34 and the substrate 20.

Abstract: An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on.

Abstract: This is a new hybrid integrated circuit. The device may be an uncooled infrared detector, with the detector comprising: uncooled infrared elements on a first substrate; internal IC structures on a second substrate to be connected to the uncooled infrared elements: IC interlevel insulation on top of the internal IC structures: IC top level metal connections on top of the IC interlevel insulation: a protective overcoat over the IC top level metal and the IC interlevel insulation; a dry etch protective layer over the protective overcoat; thermal isolation mesas on the protective layer; and local interconnects over the thermal isolation mesas and the substrate, wherein the uncooled infrared detectors are connected to the internal IC structures through the local interconnects. In addition, the protective layer may include a photosensitive polyimide, a plasma deposited silicon dioxide (SiO.sub.2), a colloidal SiO.sub.2, a PMMA or a PIRL.

Abstract: A method and system have been described for simultaneously controlling one or multiple metrics of non-uniformity using a model form independent multi-variable controller.

Abstract: Thermal imaging system (10) includes a focal plane array (18) having pixels (20). Signals produced by pixels (20) are addressed by integrated circuit substrate (22) and passed to video processor (24). Video processor (24) includes, among other modules, a detection and substitution module (28) that detects defective pixels (21) and substitutes the signals produced by defective pixels (21). The detection and substitution of signals produced by defective pixels (21) may be performed while viewing the thermal scene (12) or while stimulating pixels (20) with a stimulus. A thermal stimulus may be generated by a thermoelectric cooler (50) thermally coupled to integrated circuit substrate (22) and focal plane array (18). An electrical stimulus to identify defective pixels (21) may also be delivered to pixels (20) of focal plane array (18).

Abstract: An interconnect structure and method is described herein. First, interconnect lines 14a-d are formed on a semiconductor body 10. Then, a dielectric layer 20 is coated over the semiconductor body and the interconnect lines 14a-d to a thickness sufficient to more than fill the gaps between adjacent interconnect lines. The dielectric layer 20 is baked and then cured at a elevated temperature greater than the baking temperature. By using baking, then curing, the dielectric layer 20 inside the gaps has a lower density than that above interconnect lines and that in open fields. The removal of dielectric layer from the top of the interconnect lines by etchback is optional. Finally, a layer of silicon dioxide 12 is deposited over the interconnect lines 14a-d and the dielectric layer 20. In one embodiment, contact vias 11 are then etched through the silicon dioxide 12 and dielectric layer 20 to the interconnect lines 14a-c. Preferably, the dielectric material is spun on.

Abstract: This is a system and method of etching pyroelectric devices post ion milling. The method may comprise: forming a mask 32 for thermal isolation trenches on a substrate 14; ion milling thermal isolation trenches 40 in the substrate 14; and etching undesired defects 44 caused by the ion milling by applying a dry etch, a solvent etch, or a liquid etch to the trenches. The etch may include: hydrofluoric acid, perchloric acid, a solution of a chlorine salt and water which is then exposed to ultraviolet light or any similar chemical solution giving the correct reducing properties. The mask 32 and ion milling may be applied from either the front side or the back side of the infrared detector.

Abstract: This is a system and method of fabricating hybrid integrated circuits (IC). The method may comprise: forming internal IC structures on a substrate; forming IC interlevel insulation on top of the internal IC structures; forming IC top level metal connections on top of the IC interlevel insulation; depositing a protective overcoat over the IC top level metal and the IC interlevel insulation; depositing a dry etch protective layer over the protective overcoat; and dry etching the etch protective layer and the protective overcoat to expose portions of the IC top level metal. The deposition of the protective overcoat may include depositing silicon dioxide or silicon nitride. In addition, the deposition of the dry etch protective layer may include depositing a photosensitive polymide layer. Furthermore, the dry etching may include photolithography.

Abstract: This is a vertical field-effect resonant tunneling transistor device comprising: a semi-conducting substrate 46; a drain region 48 above the semi-conducting substrate; a multiple-barrier multi-well resonant tunneling diode 52, 54, 56, 58, 60 above the drain layer; a two dimensional electron gas heterostructure 64 above the multiple-barrier multi-well resonant tunneling diode; a source region 72 extending through the two dimensional electron gas and above the multiple-barrier multi-well resonant tunneling diode; ohmic contacts 70 on the source region, wherein the source region provides an ohmic connection to the two dimensional electron gas; and gate s! 68, 74 besides the source region.

Abstract: This is a device and method of forming such, wherein the device has an amorphous "TEFLON" (TFE AF) layer. The device comprising: a substrate; a TFE AF 44 layer on top of the substrate; and a semiconductor layer 42 on top of the TFE AF 44 layer. The device may be an electronic or optoelectronic device. The semiconductor layer may be a metal or other substance.

Abstract: A method of fabricating a transistor on a wafer including: forming a doped transistor body 42 on top of an insulator 34; doping source/drain regions in the transistor body; forming a gate oxide 44 on top of the transistor body; forming sidewall spacers along the transistor body; depositing a metal layer over the transistor body; forming an amorphous silicon layer over the metal layer, the amorphous silicon layer patterned in a gate and a local interconnect configuration; annealing to form silicided regions above the source/drain regions within the transistor body, and where the metal layer reacts with the amorphous silicon layer to create a silicided gate 50 and a silicided local interconnect 50; and etching unsilicided portions of the metal layer to leave silicided source/drain regions, a silicided gate, and a silicided local interconnect.