Abstract: A binary signal is first digitally transformed to obtain both an altered binary signal and its complement. The altered and altered complementary signals are next each delayed by two bit intervals of the original waveform to obtain both delayed altered and delayed altered complementary signals in binary form. Then, the altered and delayed altered complementary signals are gated to obtain the first gated binary output signal wherein a second level output signal is obtained whenever the two input signals are both first level signals and the first gated signal is a first level signal for all other input combinations. The altered complementary and delayed altered signals are similarly gated to obtain a second gated output signal in binary form. Finally, the first and second gated output signals are compared to obtain a three-level digital modified duobinary signal.

Abstract: The one-port network here includes a pair of terminals and a single differential input operational amplifier having an output electrically connected through a resistor R3 to a first input of the amplifier, through a resistor R4 to a second input of the amplifier, through a resistor R7 to one terminal of the network, and through the series combination of the resistor R3 and a resistor R5 to the other terminal of the network which is also electrically connected to a ground reference potential. The second input of the amplifier is also connected to ground through a resistor r6. The first and second inputs of the amplifier are also electrically connected through the series combination of a resistor R1 and capacitor C1 and through a resistor R2, respectively, to the one network terminal.

Abstract: The one-port network here includes a pair of terminals having a resistor R7 electrically connected therebetween, and a differential-input operational amplifier having an output electrically connected through a resistor R3 to a first input of the amplifier and through a resistor R4 to a second input of the amplifier. The first input of the amplifier is connected through a capacitor C5 to one terminal of the network which is electrically connected to a ground reference potential. The second input of the amplifier is also connected to ground through a resistor R6. The first and second inputs of the amplifier are electrically connected through resistor R1 and capacitor C2, respectively, to the other terminal of the network.

Abstract: Inverted and noninverted representative dial pulse signals are coupled to associated semiconductor diodes which are connected to opposite sides of a first timing capacitor, each side of the first capacitor being connected through a different associated timing resistor to a supply voltage and connected to an input of an associated NOR-gate. The output of each NOR-gate is coupled to an input of the other NOR-gate. A corrected dial pulse signal is the output signal of one NOR-gate. This output signal is also coupled through the series combination of a second timing capacitor and associated timing resistor to the supply voltage and through the second capacitor and an inverter to another input of the one NOR-gate. A corrected dial pulse signal with a corrected break pulse interval is not produced for an input dial pulse signal having a break pulse interval with a duration of less than a first time interval which is set by the first capacitor, an associated resistor, and the threshold level of the one NOR-gate.

Abstract: A panel for selectively locking pairs of elongated mating connectors together in a connected relationship including a pair of symmetrically shaped plates that are rigidly supported in a spaced-apart and parallel relationship by a pair of channels extending therebetween. One connector of each pair is rigidly attached to first legs of the two channels by screws. The other connector of each pair is plugged into an associated one connector and has an elongated surface that is spaced from the latter. Generally rectangularly shaped holes in the plates are positioned and shaped to receive the ends of a locking bar and support it between the plates such that rotation of the bar in one direction provides over-center cam action which forces the bar into contact with the elongated surfaces of the other connectors to hold them in place. Disconnection of connectors is accomplished by rotating the locking bar in the opposite direction and removing a second connector from a first connector and the panel.

Abstract: A direct current power supply is capable of delivering up to 1 ampere at 60 to 80% power efficiency from a storage battery source, providing a positive DC power output free from inductor-generated type switching transients. The converter embodies a regenerative switching mode means which alternately drives two sets of paired power transistors, turning on each one pair of power transistors for one-half cycle. Each one of the power transistor pair alternately transfers electron charges to a first one of two switch-coupled capacitors, thence to the second one of the two capacitors, and then to a positive voltage terminal. RC clipping circuitry is coupled to each one of the pair of power transistors providing faster resetting times for the power transistors, increasing the converter power efficiency by decreasing storage-time delay. By decreasing power transistor direct shorting time during power transistor switching between transistor pairs, power loss is decreased.

Abstract: An incoherent adaptive transversal equalizer for the receiver of a differentially phase-modulated data transmission system wherein a pair of tapped delay lines are located in memory of a digital computer or central processor which performs equalization of a sampled data signal according to the mean-square error algorithm defined by equations (1) - (4). In-phase and quadrature-phase tap gains c.sub.-.sub.n and d.sub.-.sub.n are each selectively combined with both the in-phase and quadrature-phase sampled signal component words A.sub.k.sub.+n and B.sub.k.sub.+n, respectively, at associated tap lines of the delay lines (except the principal or center tap line, where n = 0 here) to produce a plurality of weighted tap signals c.sub.-.sub.n A.sub.k.sub.+n ; -d.sub.-.sub.n B.sub.k.sub.+n ; c.sub.-.sub.n B.sub.k.sub.+n, and d.sub.-.sub.n A.sub.k.sub.+n. These weighted tap signals and the center tap line signals A.sub.k.sub.+0 and B.sub.k.sub.

Abstract: The input waveform is applied via an input resistor to the inverting input of an operational amplifier. The non-inverting input is grounded. In the preferred embodiment, two feedback networks, each comprising a diode and resistor network, are connected between the output and the inverting input of the amplifier. The diodes are oppositely poled. A capacitor is connected to ground at one end and to a charging resistor at the other. The other end of the charging resistor is connected to a junction formed by the resistor and diode in one of the feedback loops. The charging resistor is selected so that the value of the voltage for the reference which is supplied by the voltage across the capacitor C, e.sub.c, is of the value to obtain the percentage clipping desired. A discharge resistor is selected so that the capacitor and discharge resistor has a long time constant with respect to the input frequency of the waveform.

Abstract: The present invention provides means for deriving a single frequency signal from logic signals A(t) and B(t) by first applying the logic signals to a combining arrangement, which includes logic circuits and can be built using only standard integrated circuit components, e.g., flip-flops, gates, and amplifiers. The output of the combining means is the sum and difference frequencies, in digital form, of the logic signals A(t) and B(t). The single frequency is selected from the frequencies present at the output of the combining means.

Abstract: Box capacitors are loaded onto an in-line track feeder with the capacitor leads extending downward between a pair of tracks. Vibration of the tracks moves the capacitors thereon so that the capacitor leads pass between the meshing teeth of a drive gear and an idler gear that is caused to turn by the former. The tracks are spaced from the gears to prevent damping of vibrations of the former. The leading edges of the teeth on the gears have a radius thereon for providing smooth feeding action of the capacitor leads between the gear teeth. The drive gear also has a chamfer on the top edges of the teeth thereof to reduce the possibility of jamming on components with bent leads. A disk is attached to the underside of the idler gear for cutting the component leads to a prescribed length as they pass between the disk and the drive gear. The ends of the teeth on the idler gear are truncated such that a cut lead is compressed into a valley between teeth on the drive gear to thereby straighten these leads.

Abstract: A time division multiplex system includes a status channel as well as a plurality of information channels and a frame synchronization channel in each frame. A submultiplexer combines a "winking" framing pulse with four different status signals to derive a four-state code. One state of the code contains a "winking" submultiplexer framing signal, and the other states transmit status information to control system alarm and restoral conditions.

Abstract: In a disconnect circuit including a pair of transistor switches that are connected in series between associated lines of a cable pair and a subscriber carrier charging circuit for selectively blocking central office battery line current to the latter during ringing of a physical subscriber handset and when the latter is off hook and is dialing, the capacitor controlling delayed turn-on of the switches is coupled thereto through a capacitive multiplier circuit. A first resistor, Zener diode, and second resistor are connected between the cable pair input sides of the switches. A control transistor is connected between the base electrodes of the switching transistors and one side of the diode. The capacitive multiplier here comprises a pair of transistors connected as a Darlington compound between the capacitor and diode for converting a variable input current to a constant low-level current for charging the capacitor, the multiplier transistors bypassing the remainder of this input current.