Abstract: A field programmable gate array (FPGA) device includes a high-speed serializer/deserializer (SERDES). The field programmable gate array allows programmable built-in testing of the SERDES at operating speeds. A digital clock manager circuit allows clock signals coupled to the SERDES to be modified during the test operations to stress the SERDES circuit. The logic array of the FPGA can be programmed to generate test patterns and to analyze data received by the SERDES circuit. Cyclic redundancy check (CRC) characters, or other error checking characters, can also be generated using the logic array. During testing, the FPGA can perform extensive tests on the communication circuitry and store the results of the testing. An external tester can read the results of the test without substantial test time or complicated test equipment. After testing is complete, the device may be re-programmed to perform the end-user function, adding zero cost to the device for test implementation.

Abstract: A differential amplifier amplifies input signals and includes first and second differential input transistor pairs. The first input pair controls output voltages by adjusting sink currents coupled to the outputs. The second pair of transistors compliments the first pair by dynamically adjusting a current sourced to the outputs. A common mode circuit has also been described that adjusts both the current sourced to the outputs and the sink currents. In one embodiment, the amplifier is fully differential and controls both current source transistors and current sink transistors coupled to the amplifiers outputs.

Abstract: A differential comparator having offset correction and common mode control providing stable op amp output that changes only due to the original inputs coming into the comparator. The difference comparator has increased common-mode difference tolerance, and large op-amp offset tolerance, as well as fast decision time.

Abstract: A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

Abstract: A translator includes an initial circuit device configured to charge a translator output to a first voltage level in response to a change in an input signal. The translator further includes a sensing device configured to detect the output's potential approaching the first voltage level and smoothly shift charging functions over to a secondary circuit device, which will continue to charge the output up to a second voltage level.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of addressable blocks. Control circuitry is provided to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks. The control circuitry performs the write or erase operation in response to an externally provided command sequence and prohibits the write or erase operation if an externally provided bank address changes during the externally provided command sequence.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The memory automatically provides status data when a read command is received for a memory array location that is currently subject to a write operation. The automatic status output allows multiple processors to access the memory device without substantial bus master overhead. The memory can also output status data in response to a status read command.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory includes a clock connection to receive an external clock signal, a chip select (CS#) connection to receive a chip select signal, a row address strobe (RAS#) connection to receive a row address strobe, a column address strobe (CAS#) connection to receive a column address strobe and a write enable (WE#) connection to receive a write enable signal. Control circuitry is provided to perform a burst read operation of memory cells in a first block of the memory and interrupt the burst read operation when the chip select signal is active, the row address strobe is either inactive or active, the column address strobe is de-active, the write enable signal is active, and the address signals identify the first block simultaneously during the burst read operation.

Abstract: Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device can detect a brown-out of a supply voltage. The memory device comprises a voltage detection circuit to monitor a supply voltage and provide a signal if the supply voltage drops below a predetermined value. A latch is coupled to the voltage detection circuit and can be programmed to indicate if the supply voltage dropped below the predetermined value. An external controller can read a status of the latch. The memory, therefore, can provide an indication to an external controller that a reset, or initialization, operation is needed.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged to an initial voltage level prior to reading the memory cell. The nodes can be pre-charged by charge sharing multiple bit lines. A reference current is coupled to a selected sensing node to increase the voltage potential of that node. At the same time, a word line signal is provided to a memory cell coupled to the selected node. If the memory cell is programmed, so that that it does not conduct current in response to the word line signal, the reference current increases the selected node such that the differential voltage sensing circuit can sense a differential between the two nodes. If the memory cell is not programmed, the memory cell conducts enough current to both discharge the selected sensing node and sink the reference current.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc.

Abstract: A compact disc handler includes a picker elevator containing a helically threaded lead screw journaled for rotation about a vertical axis and having a traveling nut thereon to which a disc picker arm is attached. A guideway in the tower cooperates with the picker arm to constrain the picker arm from rotating until reaching a predetermined height elevator. Using this design, a CD can be retrieved from an input hopper, placed in a label printer or other CD publishing/playing device and upon completion of same operation on the disc, it is transported by rotation to an output hopper.

Abstract: A memory device can read data stored in memory cells using a differential voltage sensing technique. The memory includes a differential voltage sensing circuit having two input nodes. The nodes of the sensing circuit are pre-charged prior to reading the memory cell. The nodes are pre-charged by charge sharing multiple bit lines. In one embodiment, local bit lines having a first charge are coupled to global bit lines having a second charge to provide a desired pre-charge level. The local and global bit lines can have equal capacitance values. The voltages of the bit lines prior to charge sharing can be any selected value, but in one embodiment the local bit lines are discharged to ground and the global bit lines are charged to Vcc. The memory includes a programmable fuse circuit to selectively activate pass circuitry and couple one or more local bit lines to a global bit line in response to the pass command code. This allows the pre-charge level of the sensing nodes to be adjusted after fabrication.

Abstract: A memory device has multiple selectable read data paths. Some of the read data paths include compression circuitry to compress data and decrease test time by testing multiple memories in parallel and/or multiple array banks from the same memory in parallel. A non-compression read path is provided to by-pass the compression circuitry. During memory read operations, therefore, data can be coupled to output buffers without being subjected to delays through a compression circuit. A first compression path can be selected to couple 16 bits from 1 memory array bank to 4 output connections. A second compression path can be selected to couple 64 bits from 4 memory array banks to 4 output connections.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of addressable blocks. Control circuitry is provided to access the plurality of addressable blocks to perform a write or erase operation on memory cells contained in a first one of the plurality of addressable blocks. The control circuitry performs the write or erase operation in response to an externally provided command sequence and prohibits the write or erase operation if an externally provided bank address changes during the externally provided command sequence.

Abstract: A memory device provides a more efficient address decoding operation. In one embodiment, the memory device is a synchronous flash memory that has an array of memory cells arranged in rows and columns. An external device, such as a processor, provides row and column addresses for accessing the memory array. The memory device can include the internal address counter, such as a burst counter. The address processing circuitry includes address input buffers having a first latch circuit coupled thereto, and a multiplexer coupled to receive either the input address signals or addresses generated by the internal address counter. Second latch circuits are coupled to the multiplexer circuits. The second latch circuits, in one embodiment, latch the externally provided address signals coincident with the first latch circuit.

Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. In one embodiment, the present invention can include a memory device comprising an array of memory cells arranged in addressable blocks and an n-bit status register. The memory includes a control circuit coupled to the n-bit status register to program a first bit of the n-bits to a first state indicating if a program operation is being performed on the array. The control circuit further programs second and third bits of the n-bits to identify one of the addressable blocks while the array is being programmed. A method of operating a memory device includes initiating a write operation on a first programmable location of the memory device using a first processor, and reading a status from status data stored in the memory device during the write operation. The status indicates an identification of the first programmable location.