Abstract: In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions.

Abstract: In general, in one aspect, the disclosure describes an apparatus comprising a low leakage latch to store a state of a circuit during inactive periods. The state is transferred to the low leakage latch upon receipt of an inactive pulse. A buffer is used to receive the state from an output of the low leakage latch and to isolate the state. State restore circuitry is used to restore the state to the circuit when the circuit returns to an active mode. The state restore circuitry is used to receive the isolated state and to restore the state upon receipt of an active pulse.

Abstract: In general, in one aspect, the disclosure describes a switching device that includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler incorporates a mechanism to periodically monitor its operating efficiency and perturb its internal state when its efficiency is below a certain desired level.

Abstract: In general, in one aspect, an apparatus includes a phase frequency detector, a charge pump, a voltage controlled oscillator, an integral capacitor to maintain an integral charge and provide an integral voltage, and a mutual-charge canceling sample reset (MCSR) capacitor to maintain a proportional charge and provide a proportional voltage each reference clock cycle. The MCSR includes a first proportional capacitor, a second proportional capacitor in parallel to, and having substantially identical capacitance value as, the first proportional capacitor, a first set of switches to provide direct coupling of the first and second proportional capacitors, and a second set of switches to provide cross coupling of the first and second proportional capacitors. The first and second set of switches alternatively turn on and off every reference clock cycle so that set of switches coupling the first and second proportional capacitors alternates every reference clock cycle.

Abstract: In some embodiments a semiconductor device is described that includes, on a single die, both a functional circuit and a power-gating circuit. The power-gating circuit may be used to control the power delivered to core circuit elements on the semiconductor device. The power may be provided to and possibly from the power-gating circuit using underutilized die connection elements. Other embodiments are otherwise disclosed herein.

Abstract: In general, in one aspect, the disclosure describes a method including determining a change in a lock state of a phase lock loop (PLL). Current provided to a charge pump (CP) is adjusted based on the change in the lock state of the PLL. The adjusting of the current is synchronized to occur during an idle state of the CP.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having at least one ingress switch module to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switch module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes at least one egress switch module to receive the wavelength division multiplexed signal from the core switch module and to transmit data.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a memory device having a plurality of memory cells. An inverter is used to invert data and tag information destined for the memory device. A register is used to capture the inverted data and tag information. A write inverted value logic is used to determine when to enable writing the inverted data and tag information from the register to the memory device. When inverted data and tag information is written to a memory cell the memory cell is invalidated.

Abstract: In general, in one aspect, a switching device includes a plurality of ingress ports to receive data from external sources and a plurality of egress ports to transmit data to external destinations. The switching device also includes a plurality of queues to store data waiting to be transmitted from a particular ingress port to a particular egress port. A request generator generates requests for permission to transmit data for the queues. A request indicates a cumulative amount of data contained in a respective queue. A switching matrix provides selective connectivity between the ingress ports and the egress ports. The switching device further includes a scheduler to receive the requests, generate grants based thereon, and configure the switching matrix. The scheduler operates on a pipeline schedule and modifies the requests received to account for grants generated in current period or previous period not reflected in the queues.

Abstract: In general, in one aspect, the disclosure describes an apparatus including a memory cell. Ground biased write control circuitry is used to bias write and writebar bitlines when the memory cell is not performing a write operation. Ground biased read control circuitry is used to bias a read bitline when the memory cell is not performing a read operation.

Abstract: In general, in one aspect, the disclosure describes a localized IC thermal sensor. The thermal sensor includes an array of analog thermal sensors distributed across a circuit die to provide localized thermal measurements across the circuit die. The analog thermal sensors generate a frequency which is functionally dependent on temperature.

Abstract: In general, in one aspect, the disclosure describes an apparatus capable of queuing and de-queuing data stored in a plurality of queues. The apparatus includes a status storage device to track status for each of the plurality of queues, a status cache to track status for a subset of the plurality of queues that are undergoing processing, and a queuing engine to queue incoming data and de-queue outgoing data. The queuing engine receives and updates the status for the subset of the plurality of queues from the status cache and receives and updates the status for remaining queues from the status storage device.

Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: In general, in one aspect, the disclosure describes an apparatus for engineering di/dt. The apparatus includes a plurality of functional blocks to perform different functions. The apparatus also includes a clock source to provide a clock signal to said plurality of functional blocks. At least one gating device is used to regulate application of the clock to the plurality of functional blocks. A controller is included to control the at least one gating device and turning-on of the clock signal.

Abstract: In general, in one aspect, an apparatus includes an optical bus arm and a ring resonator arm. The apparatus also includes first, second and third directional couplers between the optical bus arm and the ring resonator arm. A first tuner is included on one of the optical bus arm and the ring resonator arm between the first directional coupler and the second directional coupler. A second tuner is included on other of the optical bus arm and the ring resonator arm between the second directional coupler and the third directional coupler. A tuning mechanism is also included.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having at least one ingress switch module to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switch module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes at least one egress switch module to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The at least one ingress switching module and the at least one egress switching module are capable of replicating multicast data packets.

Abstract: In some embodiments an apparatus to hold shower curtains is disclosed. The apparatus includes a shower bar and mounting brackets. The mounting brackets are connected to at least one wall to receive the shower bar. The shower bar may be made of a flexible material that has a rectangular cross section and a rounded upper edge. The rectangular cross section enables the shower curtains to lay flat on the bar. The flexible material may enable the shower bar to be flexed during installation or to absorb contact from an object. Other embodiments are otherwise disclosed herein.

Abstract: In general, in one aspect, the disclosure describes a multi-stage switch having a plurality of ingress switching modules to receive data and to generate frames that are transmitted as a wavelength division multiplexed signal. The multi-stage switch further includes a core switching module operatively connected to receive the wavelength division multiplexed signal from the at least one ingress switch module and to switch the frames. The multi-stage switch additionally includes a plurality of egress switching modules to receive the wavelength division multiplexed signal from the core switch module and to transmit data. The multi-stage switch is capable of detecting faulty paths and transmitting data through fault-free paths.

Abstract: In general, in one aspect, the disclosure describes a semiconductor device that includes a functional circuit and a dc-to-dc power converter. The power converter converts, regulates, and filters a DC input voltage to produce a DC output voltage and provides the DC output voltage to the functional circuit. The dc-to-dc power converter has an operating frequency above 10 MHz.

Abstract: In general, in one aspect, the disclosure describes an apparatus that includes a first switched capacitor comparator to be charged to a first reference voltage and to compare an input signal to the first reference voltage and to generate a first output signal when the input signal reaches the first reference voltage. A second switched capacitor comparator to be charged to a second reference voltage and to compare the input signal to the second reference voltage and to generate a second output signal when the input signal reaches the second reference voltage. Time between the first output signal and the second output signal is slew rate of the input signal.