Patents Represented by Attorney Ryuka
  • Patent number: 8324947
    Abstract: Provided is an output apparatus that outputs an output signal corresponding to an input signal, comprising a plurality of drivers that each output an intermediate signal having a waveform corresponding to the input signal; an adding section that adds together the intermediate signals output from the drivers and outputs the result as the output signal; and a control section that controls a difference in delay amount, which is from when the input signal begins to change to when the intermediate signal begins to change, among the drivers according to a designated slew rate.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: December 4, 2012
    Assignee: Advantest Corporation
    Inventor: Hiroki Ichikawa
  • Patent number: 8326908
    Abstract: There is provided a scaling operator for calculating a quotient in a first residue format obtained by dividing an input number in the first residue format by a second modulus in a residue number system for representing numbers by the first residue format of a set of residues obtained with respect to first modulus and residues obtained with respect to second modulus, having a subtracter for outputting inter-moduli values of difference which are values of difference between the residues obtained with respect to the first modulus and the residues obtained with respect to the second modulus and a quotient outputting section for outputting a set of residues of the quotient obtained with respect to the first modulus and residues of the quotient obtained with respect to the second modulus as the quotient based on the inter-moduli values of difference.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: December 4, 2012
    Assignee: Advantest Corporation
    Inventors: Kazuyuki Maruo, Takahiro Yamaguchi
  • Patent number: 8325547
    Abstract: A test apparatus that tests a memory under test, comprising an address fail memory that stores address fail data for each address; a block fail memory that stores block fail data for each block; a reading section that reads the address fail data from the address fail memory for each block; a row fail counter that, for each row address in a group including a plurality of the blocks in the memory under test, counts the fail cells indicated by the address fail data; and a column fail counter that counts the fails cells for each column address.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: December 4, 2012
    Assignee: Advantest Corporation
    Inventor: Kenichi Fujisaki
  • Patent number: 8264196
    Abstract: A charge control apparatus for controlling how to charge a battery unit having a plurality of batteries connected in series, includes a connection control section that divides the batteries into a plurality of groups of batteries by switching connections between the batteries, according to a received current amount indicative of an amount of a current that can be received from one or more external power sources, and a charge control section that charges the groups of batteries in parallel with power received from the external power sources.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: September 11, 2012
    Assignee: The Japan Research Institute, Limited
    Inventor: Masanobu Mera