Patents Represented by Attorney S. Caserza
  • Patent number: 5353430
    Abstract: A method for operating a cache memory system which has a high speed cache memory and a mass storage device that operate in a highly efficient manner with a host device. The system operates to dynamically assign segments of the cache memory to correspond to segments of the mass storage device, accept data written by the host into portions of the assigned segments of the cache memory, and determine if the elapsed time since any modified data has been written to the cache memory exceeds a predetermined period of time, or if the number of modified segments to be written to the mass storage device exceeds a preset limit. If so, the cache memory system enables a transfer mechanism to cause modified data to be written from the cache memory to the mass storage device, based on the location of segments relative to a currently selected track of the mass storage device.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: October 4, 1994
    Assignee: Zitel Corporation
    Inventor: Marvin Lautzenheiser
  • Patent number: 5216515
    Abstract: A novel cable interconnect system provides for the overnight delivery of advertising messages to optical disc libraries located at cable headends and for the automated and customized insertion of ads on a plurality of cable systems throughout a wide geographic area. A verification and accounting system provides ad run verification and accounting information. The cable interconnect enables the delivery of commercial messages, for example via satellite, on an overnight basis from a central control facility to cable television system headends located in any desired geographic area such that a large number of cable television systems can receive the video ads simultaneously.
    Type: Grant
    Filed: May 23, 1991
    Date of Patent: June 1, 1993
    Assignee: Adexpress Company
    Inventors: Gerald G. Steele, Thomas J. Stump, James Kraenzel
  • Patent number: 5057907
    Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.
    Type: Grant
    Filed: June 11, 1990
    Date of Patent: October 15, 1991
    Assignee: National Semiconductor Corp.
    Inventors: Boon K. Ooi, Shiann-Ming Liou, Ka-Heng The, Norman L. Gould