Patents Represented by Attorney S. J. Phillips
  • Patent number: 4483003
    Abstract: A parity checking arrangement for tag information in a cache memory. Parity generation is performed on the input tag in parallel with tag memory lookup and then compared with the parity stored in tag memory in order to speed operation. A single parity generator also may be used for writing into tag memory.
    Type: Grant
    Filed: July 21, 1982
    Date of Patent: November 13, 1984
    Assignee: AT&T Bell Laboratories
    Inventor: David D. Beal
  • Patent number: 4470115
    Abstract: An improved computer program method for rapidly copying data that operates in a time-shared operating system environment. Two concurrent computer program processes are employed, each copying data from the input device to the output device through its own memory buffer. The two processes communicate with one another through interprocess communication means provided by the operating system in order to coordinate their activity. As a result, double buffered overlapped input/output is achieved using only synchronous input/output commands provided by the operating system.
    Type: Grant
    Filed: March 12, 1982
    Date of Patent: September 4, 1984
    Assignee: Bell Telephone Laboratories Incorporated
    Inventor: Larry A. Wehr
  • Patent number: 4466060
    Abstract: An adaptive distributed message routing algorithm that may be implemented in a computer program to control the routing of data messages in a packet message switching digital computer network. Network topology information is exchanged only between neighbor nodes in the form of minimum spanning trees, referred to as exclusionary trees. An exclusionary tree is formed by excluding the neighbor node and its links from the tree. From the set of exclusionary trees received a route table and transmitted exclusionary trees are constructed.
    Type: Grant
    Filed: February 11, 1982
    Date of Patent: August 14, 1984
    Assignee: AT&T Bell Telephone Laboratories, Incorporated
    Inventor: Guy G. Riddle
  • Patent number: 4443876
    Abstract: Parity for the address of a low order zero in an input data word is generated directly from the input data rather than from the address of the low order zero. A find low order zero circuit (11) generates an address of the low order zero in the data word. Simultaneously with this operation a parity generating circuit (12) operates on the input data word to generate parity for the low order zero address. The parity generating circuit comprises a plurality of individual circuits (30 through 33) each of which operates on a different byte of the input data word. The individual circuits each generate a control signal (E.sub.a,E.sub.b . . . ) according to whether or not its byte contains a low order order zero, and a result signal (R.sub.a,R.sub.b . . . ) which represents the parity of the address of the low order zero, if any, in the byte taking into account the byte position in the input data word. Logic circuitry combines the control and result signals to form the overall parity for the low order zero address.
    Type: Grant
    Filed: August 31, 1981
    Date of Patent: April 17, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Ying-Wah Ng
  • Patent number: 4405983
    Abstract: A microprocessor system that provides protection against memory violations by interrupting the central processing unit (CPU). A problem arises when the interrupt itself causes memory violations in push-down stack operations. This problem is solved by providing an auxiliary memory to store stack overflow data. Memory violations are detected (30, 40) and overflow data is written (42, 60, 33, 100) into auxiliary memory, at sequential locations (50, 51, 60). An interrupt signal is returned (30, 20) to the CPU. A stack overflow interrupt program reads the number of locations written (50, 80, 90), and accesses the auxiliary memory (100, 60, 70, 90) to determine and correct the cause of the overflow.
    Type: Grant
    Filed: December 17, 1980
    Date of Patent: September 20, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Pedro I. Perez-Mendez
  • Patent number: 4379205
    Abstract: A speech scrambling system using discrete prolate spheroidal sequence coefficients (PC). The problem is to provide high fidelity and high security in a scrambling system while limiting the bandwidth of the scrambled signal to the bandwidth of the original speech signal. The disclosed system uses PC to solve this problem. The analog speech signal is digitally sampled (100), converted to PC (203, 204, 205), scrambled (208, 209), and converted to scrambled samples (211, 212, 213). The scrambled samples are transmitted using pulse amplitude modulation (102) in the same bandwidth as the original signal. At the receiving end, the inverse steps are performed to recover the original speech. The scrambling is periodically modified (220, 320) to improve security.
    Type: Grant
    Filed: June 22, 1979
    Date of Patent: April 5, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Aaron D. Wyner