Abstract: A phase-lock-loop circuit of a two-loop deflection arrangement is located in a first integrated circuit. The phase-lock-loop circuit generates a first signal at 32Xf.sub.H that is capacitively coupled to a tank circuit. A regenerative amplifier stage that is located in a second integrated circuit has an input terminal that is coupled to the tank circuit and an output terminal for producing a second signal. During normal operation, the second signal is synchronized to the first signal. The second signal is utilized in a phase-control-loop circuit of the two-loop deflection arrangement for generating a synchronized deflection current in a deflection winding.

Abstract: A first pair of transistors, Q721 and Q723, operating, each, as an emitter follower, has a relatively low emitter current. The emitter followers drive corresponding base electrodes of transistors of a second pair of transistors, Q148 and Q149, coupled as a differential amplifier. A current gain compensating transistor Q726 has a current gain that tracks current gain variations of each of the transistors of the second pair. A base electrode current of the compensating transistor and a second current i.sub.Q727 that is unaffected by current gain variations are summed. The summed current is coupled via transistors Q722 and Q724 of a current mirror arrangement to first and second junction terminals, 610e and 610f. The junction terminals are coupled between the respective emitter electrodes of the emitter followers and the base electrodes of the second pair.