Abstract: A set of identifiers (for example, the name of a party and the associated telephone number) is stored in the memory of telephone apparatus. Sequential retrieval of the stored identifiers is facilitated by the use of a prominent button that is oversized relative to the size of the buttons of a conventional telephone keypad. Retrieved identifiers are indicated visually, aurally, and/or tactilely. Selection of an indicated identifier initiates a call to the party represented by the identifier.

Abstract: A low noise transistor IC or module comprises a plurality of conventional CMOS transistors which are laid out in parallel in such a way that the effective gate width of the combination of transistors is increased, yet the effective gate resistance and hence the noise figure (NF) of the circuit are reduced. A low noise amplifier incorporating such a module is also described.

Abstract: A method of detecting whether a valid DS1 signal is being received by a receiver. If the receiver does not have a valid signal (loss of signal), then the receiver reads consecutive fixed sized N bit blocks of the received digital signal. Each of the blocks or windows is checked for minimum 1s density. Received consecutive 0s are counted and checked against a maximum. If two sequential blocks of bits satisfy the 1s and consecutive 0s tests, then the received signal is judged valid and an acquisition of signal flag is asserted.

Abstract: A reduced loss coupling technique for combining multiple, parallel, gain-stages to form an amplifier. A first transmission line, with multiple taps, couples the inputs of the gain-stages together and to an input port for the amplifier. A second transmission line, also with multiple taps, couples the outputs of the gain-stages together and to an ouput port for the amplifier. Preferably, the output port is connected to the end of the second transmission line while the input port is connected asymmetrically (off center) along the first transmission line. The actual position of the input port along the first transmission line is determined by the desired amount of phase mismatch of between signal paths through all of the gain-stages as measured from the input port to the output port.

Abstract: Technique for adding a dither signal to a sigma-delta modulator to remove low level tones and periodic noise in the desired passband of the modulator when no, or a very low, signal is present (idle). The dither signal is a high-level signal added to the imput of an quantizer in the modulator, the normalized power in the AC component thereof being at least about ##EQU1## of the square of the quantizer step, where N is the order of the modulator. No significant reduction in the dynamic range of the modulator results. The technique may also be applied to multiple order sigma-delta modulators as well as to multiple stage sigma-delta modulators. Further, the dither may be added at any point in the modulator with suitable filtering of the dither. The transfer function of the filter is proportional to the noise shaping transfer function of the modulator between the point of addition of the dither and the input to the quantizer.

Abstract: A bipolar or field-effect transistor amplifier with very large dynamic range for use as a preamplifier in a radio receiver, optical link reciver, or the like. The amount of gain is approximately an integral number. Diode-connected transistors in the collector load circuitry of a gain-providing transistor cancel the distortion from the non-linear effects of the emitter-base junction of the gain-providing transistor at high input signal levels. The number of diodes corresponds to the amount of gain desired. To reduce the noise generated by the amplifier, the emitter of the gain-providing transistor has an inductor in series therewith and the collector load circuitry has an inductor therein, the ratio of the inductances substantially determining the gain of the amplifier.

Abstract: An oscillator, such as a crystal oscillator, is presented for low jitter (low phase noise) applications, such as in frequency synthesizers or digital repeaters. The two terminals of a resonator are coupled to the input and output of an amplifier, the amplifier together with other components effecting a negative impedance. The inputs of a comparator are connected to the terminals of the resonator. The output of the comparator, preferably differential, is a signal having a frequency substantially determined by the resonator.

Abstract: A process for manufacturing selectively doped heterostructure field-effect transistors (SDHTs), a desired wafer structure for SDHT fabrication and a method for isolating SDHTs on the wafer are disclosed herein. The wafer has epitaxial layers grown on a substrate. The layers are: a buffer layer of GaAs, a first spacer layer of AlGaAs, a donor layer of AlGaAs, a second spacer layer of AlGaAs, a first cap layer of GaAs, an etch-stop layer of AlGaAs and a second cap layer of GaAs. A protective layer of AlGaAs may then be grown on the second cap layer to protect the second cap layer from contamination or damage. Also a superlattice may first be grown on the substrate.This invention was made with Government support under contract No. F29601-87-R-0202 awarded by the Defense Advanced Research Projects Agency, and under contract No. F33615-84-C-1570 awarded by the Air Force Wright Aeronautical Laboratories. The Government has certain rights in this invention.

Abstract: A method of switching a switched-capacitor circuit to reduce signal-dependent distortion resulting from the switching operation. Two single-pole, double-throw switches in the array, having the switched capacitor coupling between to the common terminals thereof, are alternately switched without the use of an intermediate (no-make) state.

Abstract: A digital data receiver and digital phase-locked loop for providing rapid acquistion and decoding of burst mode data signals, such as Manchester encoded data, without ambiguity. A 180.degree. phase mis-lock detector and phase connector is provided to eliminate any phase-lock ambiguities that may occur. The mis-lock detector utilizes a Manchester data violation detector to determine if the correct phase of sample clock from the digital phase-locked loop is being used for decoding the Manchester data. The digital phase-locked loop utilizes a digital delay line with multiple taps, the appropriate tap, corresponding to a desired phase of a reference clock, is selected as the optimal sample clock. A phase detector determines the difference in phase, measured by the number of taps of the delay line, between the sampling clock phase and the incoming data transitions. The difference is accumulated in an integrator to select the optimal sampling clock phase tap.

Abstract: A lateral MOS-controlled thyristor (MCT) structure using a single MOS gate for both turn-on and turn off. By eliminating a parasitic lateral PNP transistor through the addition of a high resistivity region surrounding one output terminal, and adding a DMOS transistor to a conventional thyristor structure, the maximum turn-off current limit is increased with lower forward voltage drop than that available in prior art lateral MCTs.

Abstract: A mobile ion getterer is added to metalization layers on an integrated circuit or discrete device to reduce mobile ion contamination therein. Preferably, chromium is used as the mobile ion getterer and is added to an aluminum target used as the metal source for sputtering the chromium and aluminum onto the integrated circuit or discrete device. This technique removes the need for ultra-high purity aluminum conductors or gettering material (P-glass) in contact with the metal conductors. This technique may be used with virtually all metalization apparatus and processes used for depositing metal onto semiconductor devices.

Abstract: A technique for compensating for variations in a resistor set overall gain switched-capacitor circuits, such as high accuracy digital-to-analog converters. The variation in overall gain from the desired gain is due to the variation in the total capacitance of the capacitors, compared to the variation in the resistance of the resistor, in the circuit during manufacture. A bias circuit, with two reference voltage outputs, is adapted to have a capacitor and a fixed resistor vary one of the voltage references depending on the capacitance thereof. The voltage difference between the two voltage references varies the overall gain of the switched capacitor circuit to compensate for variations in the overall gain. Also, a switched-capacitor digital-to-analog converter utilizing the above technique is presented.

Abstract: A combined finite impulse response filter and digital-to-analog converter for converting sigma-delta over-sampled data into analog form. The filter removes out-of-band noise energy from the reconstructed analog signal resulting from the sigma-delta encoding process. The filter/converter is implemented in switched-capacitor technology. Further, a method of designing the optimum number of taps and the tap weight coefficients of the filter is given.

Abstract: A damper circuit for switching power supplies to improve the stability thereof with high efficiency. A resistor, having a value which critically damps the flyback transformer in the supply, is selectively coupled to the transformer by a switch when the switching transistor is disabled. The decoupling of the resistor when the switching transistor is on reduces power dissipation, compared to passive damping techniques, and allows integration of the damper onto the same IC as the control circuits of the supply. The damper increases the stability of the supply by absorbing excess energy not transferred to the load. The excess energy would instead be dissipated in the transistor and upsetting the control circuits of the supply, leading to instability of thereof. In addition, a clamp circuit is provided which keeps the switch from turning on due to high slew rate transients across the transformer from the turn-on of the switching transistor.

Abstract: A high speed logic circuit having extremely low propagation delays, suitable for implementation in III-V technology. A logic stage provides the desired logic function by combining a predetermined number of input FETs. The drains of the input FETs couple to a pull-up FET and form a first intermediate output of the logic stage. The sources of the input FETs couple to a pull-down FET and form a second intermediate output of the first stage. A second stage, or buffer stage, responding to the intermediate outputs of the first stage, provides sufficient drive to an output terminal of the logic gate to drive multiple loads (gates) coupled thereto. The second stage includes a pull-down FET responsive to the second intermediate output of the first stage. The second stage also includes alternative combinations of FETs and diodes to pull-up the voltage on the output terminal of the logic gate.