Abstract: The present invention features methods for assembling arrays of AMLCD tiles into tiled, flat-panel displays having visually imperceptible seams between the tiles. Flowable, polymeric adhesive layers are used between a back substrate, various optical components such as masks and polarizers, the tiles, and a front cover plate. Several unique techniques for establishing and maintaining tile-to-tile registration during assembly of the tiled, flat-panel display are presented.

Abstract: A new logic with shift switches incorporating novel parallel compressors and counters called C4 and (7,3) families. This shift switch logic deals with modulo arithmetic operations. It employs a type of special digital signals, called state signals (as a major addition to the binary signals), and a set of electronic components, called shift switches, to manipulate such signals and conduct the logic operations. A useful modulo arithmetic produces two values: a remainder and a quotient, given two small (non-negative) integers. One integer is a variable numerator represented by a set of input digital signals (including regular and/or state signals), while the other is a dominator (base or radix) provided by the shift switch circuit as a parameter. Using C4 and (7,3) devices, two novel, parallel-structured, full array, 64.times.64 floating point multiplier schemes are disclosed.