Abstract: Approaches for protecting design information are disclosed. In one approach, a request for an IP core from an integrated circuit device is received, and the request includes identification information. An identifier range is determined from the identification information. The identifier range includes a plurality of unique device identifiers identifying a plurality of integrated circuit devices that are allowed to receive the IP core. The identifier range is downloaded to the integrated circuit device, which evaluates whether or not a unique device identifier that is stored on the integrated circuit device is within the downloaded identifier range. The IP core is programmed into the integrated circuit in response to the unique device identifier that is stored on the integrated circuit device being within the downloaded identifier range.

Abstract: A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

Abstract: A method and system are disclosed. The system includes a trusted loader. The method includes downloading an IP core from a vendor to a target device. The IP core is received in an encrypted form at the target device, which can be, for example, a programmable logic device.

Abstract: A method and system for maintaining the security of design information is disclosed. The method includes generating an encrypted IP core by encrypting an IP core using a public key, downloading the encrypted IP core to a programmable logic device (PLD), and recovering the IP core by decrypting the encrypted IP core using a private key. The private key is associated with the PLD, and the public key and the private key correspond to one another. The method may further include the PLD receiving authorization information corresponding to the IP core and comparing local authorization information stored at the PLD with the authorization information.

Abstract: A method and system for pipelined decryption is disclosed. One embodiment includes a circuit having an iterative calculation section and a cipher text storage section in support of cipher block chaining (CBC) encryption mode. The iterative calculation section may be pipelined and configured to process multiple ciphertexts at once for increased throughput.

Abstract: A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

Abstract: A method and system are disclosed. The method and system provide the ability to identify a configuration bit as an essential configuration bit. The identifying that is performed uses a configuration bit definition.

Abstract: A method and system for generating a bitstream view of a programmable logic device (PLD) design are disclosed. The present invention allows for the correlation of a physical circuit description (e.g., one or more of a PLD design's essential configuration bits) and a logical circuit description (e.g., one or more of the logic elements that make up a PLD design), which can also be viewed as correlating one or more of the physical elements of the design's implementation in the PLD with one or more of the design's logical elements.

Abstract: A set of haptic elements (haptels) are arranged in a grid. Each haptel is a haptic feedback device with linear motion and a touchable surface substantially perpendicular to the direction of motion. In a preferred embodiment, each haptel has a position sensor which measures the vertical position of the surface within its range of travel, a linear actuator which provides a controllable vertical bi-directional feedback force, and a touch location sensor on the touchable surface. All haptels have their sensors and effectors interfaced to a control processor. The touch location sensor readings are processed and sent to a computer, which returns the type of haptic response to use for each touch in progress. The control processor reads the position sensors, derives velocity, acceleration, net force and applied force measurements, and computes the desired force response for each haptel. The haptels are coordinated such that force feedback for a single touch is distributed across all haptels involved.

Abstract: A multi-port Fibre Channel controller is disclosed. Such a multi-port Fibre Channel controller includes a number of Fibre Channel ports, an interface unit coupled to each one of the Fibre Channel ports, a Fibre Channel controller, and a processor. The processor is coupled to the Fibre Channel controller, and the Fibre Channel controller is coupled to control the interface unit and coupled to the subsystem interface. Such a multi-port Fibre Channel controller may be configured as a dual-port Fibre Channel controller by, for example, employing only two Fibre Channel ports (i.e., a first Fibre Channel port and a second Fibre Channel port).

Abstract: A method and a system for acquiring local signal behavior parameters (LSBPs) of a band-limited (BL) signa, for representing and processing the signal, wherein the LSBPs encode the signal's local behavior in between Nyquist rate points. Preferably, a section of a BL signal within a sampling window is represented as a truncated series of order n at a sampling moment within the sampling window. The truncated series having n+1 LSBPs as its coefficients, encoding the signal's local behavior between Nyquist rate points. Compared to the conventional approach that encodes a signal's behavior by signal samples taken at Nyquist rate points, the invention encodes more signal behavior. Discrete signal samples are obtained from the signal. The LSBPs are solved numerically such that the interpolated values of the truncated series provide the least-square fit with the discrete signal samples.

Abstract: A signal router, configured to receive information carried by a first signal and transmit the information on a second signal, is described. The signal router, using routing information it gathers, selects the second signal from a number of signals, with the first and the second signals differing in at least one physical characteristic. The signal router operates in a network of a number of such signal routers, and so each one of the signal routers is coupled to at least one of the other signal routers. The routing information is used to create a circuit from a first one of the signal routers to a second one of the signal routers. Once the circuit is created, the information is routed over the circuit. According to one aspect of the present invention, the signals are optical signals.

Abstract: A method and apparatus implement a communications protocol whereby a host application program can communicate with a computer subsystem without the use of special driver software. In this way, the application program is able to invoke virtually any vendor-unique function on a compatible subsystem controller using only standard read/write system calls. This avoids platform dependency and greatly improves the portability of the application program.

Abstract: A method and apparatus providing for an efficient solution to the multivariate allocation of resources are described. A model is formulated that derives the relationship between a set of resources and a set of refinements, wherein any of a number of resources are used to build or comprise a refinement. The model provides for at least: the resource consumption as based upon the relationship between each refinement and its set of supporting resources, a demand distribution of the refinements, and a value function. Each resource, and the refinements that it supports, generates a resource hyperplane in a demand space, and the complete set of refinements generates an intersecting set of hyperplanes forming a polytope on which resource allocation fulfills refinement demand. An expected value function is thereafter formulated and transformed into a closed form solution.

Abstract: The present invention integrates data prefetching into a modulo scheduling technique to provide for the generation of assembly code having improved performance. Modulo scheduling can produce optimal steady state code for many important cases by sufficiently separating defining instructions (producers) from using instructions (consumers), thereby avoiding machine stall cycles and simultaneously maximizing processor utilization. Integrating data prefetching within modulo scheduling yields high performance assembly code by prefetching data from memory while at the same time using modulo scheduling to efficiently schedule the remaining operations. The invention integrates data prefetching into modulo scheduling by postponing prefetch insertion until after modulo scheduling is complete. Actual insertion of the prefetch instructions occurs in a postpass after the generation of appropriate prologue-kernel-epilogue code.

Abstract: A high efficiency multi-directional airflow system for a telecommunications equipment assembly used for housing electronic apparatuses which facilitate telecommunications functionality. The equipment assembly defines an internal cavity which can be divided into a plurality of air flow channels. Each of the plurality of air flow channels captures a sub-portion of the overall volume provided by the internal cavity. The smaller volume flow channels provide a smaller cross-sectional area through which the majority of air travels. Since the cross-sectional area is smaller, the velocity of the air through the flow channels is increased. Since the air velocity is increased, the heat transfer coefficient is also increased, thus allowing for the more efficient removal of heat from the electronic apparatuses. A set of fan trays can include a plurality of fans each directionally positioned to work in series to cause air to flow through the plurality of flow channels.

Abstract: A signal processor and method of signal processing is disclosed. The signal processor includes a differentiator and an extrapolator coupled to the differentiator. The differentiator is configured to receive an input signal and to generate a vector. The input signal is band-limited. The vector includes at least one chromatic derivative. The extrapolator is coupled to the differentiator and is configured to generate an output signal.

Abstract: A system for presenting hypermedia link information. A computer-implemented method for presenting hypermedia link information is described which relates to the user the characteristics of a data file pointed to by the hypermedia link. The computer system waits for an event to occur. This event is the user or system selecting one or more hypermedia links. The hypermedia link in this scenario points to a data file about which information is to be gathered. The computer system then requests information about the data file. In one embodiment, a cue is generated to communicate information about said data file to a user. This information may be conveyed to the user by auditory or visual means, such as a pop-up information box on the user's display. A powerful and convenient system for browsing hypermedia information is thus provided.

Abstract: A fixture is provided for use in connection with a circuit board tester. The fixture can move the unit under test (UUT), against the urging or a set of springs, to a first position in which the UUT contacts all probes of the tester, for performing a first set of tests. A partial vacuum is created in the region near the probes to permit atmospheric pressure to move the UUT to the first position. A movable or actuateable limiting member is moved to a position which can engage a fixture member in a manner such that, upon movement of the UUT in a direction away from the probes, when the vacuum is released, the amount of movement is limited, to position the UUT to contact only the taller probes. The actuator may engage any of various parts of the fixture, or a pocket found therein, including support plates or lids, or may contact a surface of the UUT.

Abstract: Techniques for the efficient location of free entries for use in performing insert operations in a binary or ternary content addressable memory. As used in data communications and packet routing, such memories often rely on an organization that maintains entries of the same “length” within defined regions. The present invention keeps the free entries (holes) compacted into a contiguous subregion within each region, without requiring hole movement during deletes. These positive effects are accomplished by initially pre-filling the entire memory with a set of hole codes that each uniquely identify the holes in each region. A conventional memory write is then performed to load routing data into the memory. Typically, such routing information will not fill the entire memory, leaving unused entries (containing the region appropriate hole code) in each region. As entries need to be deleted, they are simply replaced by writing in the region-unique hole code.