Abstract: A method and apparatus for decoding a frame of interleaved information bits in a communications system, where the decoding of the frame of interleaved information bits may begin before all of the bits in the frame are received at a decoding site. The frame of interleaved information bits has a frame start time and a frame end time. The frame also includes a first fractional segment that has a start time that is the same as the frame start time and an end time that is before the frame end time.
Abstract: Reverse link busy bits are independently generated by each base station and indicate whether a base station has reached a reverse link capacity limit. A remote station combines multipath components of the reverse link busy bits in its Active Set and in response transmits a reverse link signal only when all of the reverse link busy bits indicate that the base stations in the Active Set have reverse link capacity. In an embodiment, the remote station weights the reverse link busy signals in accordance with the signal strength of the transmitting base station and determines whether to transmit based on the weighted sum of the busy signals. In an embodiment, the remote station weights the reverse link busy signals in accordance with the signal strength of the transmitting base station and determines a maximum reverse link data rate based on the weighted sum of the busy signals.
Type:
Grant
Filed:
November 19, 2002
Date of Patent:
October 19, 2004
Assignee:
Qualcomm Incorporated
Inventors:
Paul E. Bender, Matthew S. Grob, Gadi Karmi, Roberto Padovani
Abstract: Systems and techniques are disclosed wherein a gated pilot signal can be acquired by searching for a first gated pilot signal, deriving timing information from the search for the first gated pilot signal, and searching for a second gated pilot signal using the timing information. This can be implemented in a variety of fashions including a receiver with a searcher configured to generate a bit sequence, a correlator configured to correlate a received signal with the bit sequence, and a processor configured to detect a first gated pilot signal as a function of the correlation, derive timing information from the first gated pilot signal, and detect a second gated pilot signal by using the timing information to control the bit sequence generated by the searcher. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.