Abstract: A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers.The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length L.sub.max +K, with K.gtoreq.2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length L.sub.max +K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length L.sub.x of the test object and the part L.sub.

Abstract: An improved polarity hold latch is described having a set and reset capability integrated therein. As implemented, this latch provides the desired logical functions at a reduced circuit cost and power requirements. At the same time, it overcomes the need to test for and resolve potential signal race conditions. The improved latch is particularly susceptible of being implemented on a single chip.

Abstract: An improved arrangement for cooling a module packaged semiconductor integrated circuit chip having heat generating microcircuits thereon is disclosed. Enhanced cooling over prior art techniques is achieved by utilizing an interfacial layer of liquid metal alloy coated metallic dendrites, which layer is sandwiched between two facing surfaces of the chip and a heat sink. Appropriate biasing means are also provided to urge the dendritic projections into piercing engagement with the liquid metal alloy layer, the biasing means being thermally coupled between the heat sink and the module container to thereby aid in forming unitary heat transfer path from the chip to the module container. The biasing means are adapted to provide sufficient force to cause the dendritic projections to engage and retain the liquid metal alloy layer and to non-destructively force the layer to fill all available space between the chip and the heat sink.

Abstract: A multi-layered printed circuit board is disclosed having a plurality of circuitized laminations therein. The laminates are fabricated or secured by curing layers of glass cloth which have been impregnated with heat curable resins at temperatures in excess of their glass transition temperature, the point at which such material begins to distort.Those laminations which will see at least one further curing cycle, after having themselves been cured, are formed from glass cloth impregnated heat curable resin combinations having a glass transition temperature which is significantly higher than that of the heat curable materials employed to form the subsequently and singly cured laminations. In this manner, lamination shift or distortion is appreciably reduced since those laminations which undergo a plurality of "curing" cycles, only experience one excursion beyond their transition temperature. Thus, registration mismatch between any of the circuitized laminates will not exceed acceptable levels.

Abstract: A high performance channel-to-channel adapter for interconnecting two or more digital computers or digital data processors. Multiple input/output device addresses are recognized by the channel-to-channel adapter. The channel-to-channel adapter makes the proper processor-to-processor connection by matching device addresses. In particular, it interconnects for data transfer purposes the two processors for which the same device address has been received. The assignment of device addresses for processor use and the direction of data transfer are by conventions agreed to among the software systems executing on the interconnected processors. The channel-to-channel adapter does not have a view of these conventions. In the more general case, two device addresses are assigned by software convention to each processor-to-processor link, one address being used to transfer data in one direction and the other address being used to transfer data in the opposite direction.

Abstract: Data format converting apparatus is described for simultaneously converting multiple bytes of zoned decimal data to packed decimal data or vice versa. In the preferred embodiment, this format converting apparatus is obtained by adding a minimum amount of additional circuitry to a multibyte flow-through type data shifter used for providing the normal data shifting operations in a digital data processor. In particular, a zoned-decimal-to-packed-decimal conversion capability is provided by combining additional switching logic with the normal shifter switching logic for enabling the conductors for nonadjacent data fields on the shifter input data bus to be coupled to the conductors for adjacent data fields on the shifter output data bus. A packed-decimal-to-zoned-decimal conversion capability is provided by adding further switching logic for enabling the conductors for adjacent data fields on the shifter input data bus to be coupled to the conductors for nonadjacent data fields on the shifter output data bus.

Abstract: Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole.