Patents Represented by Attorney Schein & Cai
  • Patent number: 8343795
    Abstract: The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: January 1, 2013
    Inventors: Yuhao Luo, Zhi-min Ling
  • Patent number: 8302287
    Abstract: A multilayer inductor includes a bottom magnetic layer having an external conductive pattern formed on a bottom surface thereof for connection to a substrate such as a printed circuit board. The bottom external conductive pattern includes signal/power contacts and first and second inductor electrodes. A top magnetic layer includes a top external conductive pattern having signal/power contacts and inductor electrode contacts. An inductor conductive pattern formed on the top surfaces of intermediate magnetic layers disposed between the top and bottom magnetic layers are electrically coupled to each other by means of through holes to form a spiral inductor element.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: November 6, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Lu, François Hébert
  • Patent number: 8259518
    Abstract: A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: September 4, 2012
    Assignee: Sichuan Kiloway Electronics Inc.
    Inventors: Jack Z. Peng, David Fong
  • Patent number: 8255467
    Abstract: A system and method for providing device management and sharing in an Instant Messenger system is provided. An instant messenger server and an enhanced instant messenger module are operatively coupled together. The enhanced instant messenger module has an instant messenger process and a networked device process, the instant messenger process being operable to provide instant messaging functions and services to a user and the networked device process being operable to provide data from networked devices to the instant messenger server.
    Type: Grant
    Filed: December 13, 2008
    Date of Patent: August 28, 2012
    Inventors: Herman Yau, Song Yao
  • Patent number: 8207017
    Abstract: A method of fabricating a stacked dual MOSFET die package is disclosed. The method includes the steps of (a) forming a first conductive tab, (b) stacking a high side MOSFET die on the first conductive tab such that a drain contact of the high side MOSFET die is coupled to the first conductive tab, (c) stacking a second conductive tab in overlaying relationship to the high side MOSFET die such that a source contact of the high side MOSFET die is coupled to the second conductive tab, and (d) stacking a low side MOSFET die on the second conductive tab such that a drain contact of the low side MOSFET die is coupled to the second conductive tab.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: June 26, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: Sanjay Havanur
  • Patent number: 8169062
    Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: May 1, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik K. Lui, Mike Chang
  • Patent number: 8164199
    Abstract: A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: April 24, 2012
    Assignee: Alpha and Omega Semiconductor Incorporation
    Inventors: Anup Bhalla, Yi Su, David Grey
  • Patent number: 8148256
    Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: April 3, 2012
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Anup Bhalla
  • Patent number: 8117661
    Abstract: A method and system for protecting silicon IPs from unauthorized use, transfer and sale, and for hiding confidential technology information contained in silicon IPs is described. The method and system create a content-encrypted silicon IP layout database from its original layout database. Both the layout database may be GDSII files, OASIS files, or other format layout database file, in which multiple records sequentially build the layout database. In accordance with one preferred embodiment, first, the original layout database is parsed and saved as sequential records in the memory. Next, the structure records, which construct structures in the original layout database, are selected from the saved records. Once the structure records have been selected, the data of the structure records may be compressed with using a public compressing method, and may be encrypted with using a public cryptography algorithm.
    Type: Grant
    Filed: February 26, 2007
    Date of Patent: February 14, 2012
    Inventor: Weidong Zhang
  • Patent number: 8113223
    Abstract: The invention relates to a telescoping umbrella, particularly a sun or rain umbrella, having a receiving tube and a telescoping tube displaceably and lockably located therein, having an umbrella roof connected to the telescoping tube in an articulating manner, the umbrella roof being adjustable by means of a cable or Bowden wire running inside the tubes, and having an actuating device for the cable or Bowden wire, characterized in that the actuating device comprises a winch for the cable or Bowden wire, the winch being located inside the receiving tube.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: February 14, 2012
    Assignee: Yotrio Group Co., Ltd.
    Inventors: Zhonglin Wang, Kai Liu
  • Patent number: 8080330
    Abstract: A microporous separator film for electrochemical cells and a method of making such films is disclosed. The microporous separator film includes an intimate mixture of an electrically insulating matrix phase and a self-switching voltage activated conductive phase, wherein the voltage activated conductive phase provides a plurality of conductive paths from a first face of the microporous separator film to a second face of the microporous separator film. The method for making the composite microporous separator film includes the steps of forming an intimate mixture of at least an insulating matrix phase and a self-switching voltage activated phase, forming a film from the mixture, and generating pores within the film.
    Type: Grant
    Filed: May 28, 2011
    Date of Patent: December 20, 2011
    Assignee: Farasis Energy, Inc.
    Inventors: Keith Douglas Kepler, Yu Wang
  • Patent number: 8067822
    Abstract: A semiconductor integrated circuit package having a leadframe (108) that includes a leadframe pad (103a) disposed under a die (100) and a bonding metal area (101a) that is disposed over at least two adjacent sides of the die. The increase in the bonding metal area (101a) increases the number of interconnections between the metal area (101a) and the die (100) to reduce the electric resistance and inductance. Furthermore, the surface area of the external terminals radiating from the package's plastic body (106) is increased if not maximized so that heat can be dissipated quicker and external terminal resistances reduced. The integrated circuit is applicable for MOSFET devices and the bonding metal area (101a) is used for the source terminal (101). The bonding metal area may have a “L” shape, a “C” shape, a “J” shape, an “I” shape or any combination thereof.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: November 29, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Leeshawn Luo, Anup Bhalla, Yueh-Se Ho, Sik K. Lui, Mike Chang
  • Patent number: 8058727
    Abstract: A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: November 15, 2011
    Assignee: Alpha and Omega Semiconductor Incorporation
    Inventors: Tao Feng, Anup Bhalla, Yueh-Se Ho
  • Patent number: 8058961
    Abstract: A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: November 15, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Tao Feng, Xiaotian Zhang, Jun Lu
  • Patent number: 8058960
    Abstract: A chip scale power converter package having an inductor substrate and a power integrated circuit flipped onto the inductor substrate is disclosed. The inductor substrate includes a high resistivity substrate having a planar spiral inductor formed thereon.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: November 15, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Ming Sun
  • Patent number: 8053891
    Abstract: A standing chip scale package is disclosed. The standing chip scale package provides electrical connection to bumped device contacts on both sides of the chip. The package is coupleable to a printed circuit board in a standing configuration such that front and back sides of the bumped chip are substantially perpendicular to a mounting surface. A process of fabricating the standing chip scale package is also disclosed.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: November 8, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Tao Feng, Anup Bhalla, Yueh-Se Ho
  • Patent number: 8053874
    Abstract: A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source areas and a metalized gate area, a patterned source connection having a plurality of dimples formed thereon coupling the source lead to the semiconductor die metalized source areas, a patterned gate connection having a dimple formed thereon coupling the gate lead to the semiconductor die metalized gate area, a semiconductor die drain area coupled to the drain lead, and an encapsulant covering at least a portion of the semiconductor die and drain, source and gate leads.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: November 8, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ming Sun, Lei Shi, Kai Liu
  • Patent number: 8048775
    Abstract: A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: November 1, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Tao Feng, Sung-Shan Tai
  • Patent number: 7989103
    Abstract: A microporous separator film for electrochemical cells and a method of making such films is disclosed. The microporous separator film includes an intimate mixture of an electrically insulating matrix phase and a self-switching voltage activated conductive phase, wherein the voltage activated conductive phase provides a plurality of conductive paths from a first face of the microporous separator film to a second face of the microporous separator film. The method for making the composite microporous separator film includes the steps of forming an intimate mixture of at least an insulating matrix phase and a self-switching voltage activated phase, forming a film from the mixture, and generating pores within the film.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: August 2, 2011
    Assignee: Farasis Energy, Inc.
    Inventors: Keith Douglas Kepler, Yu Wang
  • Patent number: 7951651
    Abstract: A DFN semiconductor package includes a leadframe having a die bonding pad formed integrally with a drain lead, a gate lead and a source lead, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead and a die gate bonding area coupled to the gate lead, and an encapsulant at least partially covering the die, drain lead, gate lead and source lead.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 31, 2011
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Kai Liu, Xiaotian Zhang, Ming Sun, Leeshawn Luo