Patents Represented by Attorney, Agent or Law Firm Schmeiser, Olson & Watts
  • Patent number: 8270759
    Abstract: A method and system for transforming a video image from a High Dynamic Range (HDR) image on an array of pixels to a Low Dynamic Range (LDR) image. An old luminance generated from a color space of the HDR image is scaled and segmented into stripes. Each stripe has at least one row of the array. A target zone surrounding a current pixel in each stripe is determined from a search strategy selected from a linear search strategy and a zone history-based search strategy. A convolution of the scaled luminance at a current pixel of each stripe is computed using a kernel specific to the target zone. The convolution is used to convert the stripes to tone-mapped luminance stripes which are collected to form a tone mapped luminance pixel array that is transformed to the color space to form the LDR image. The LDR image is stored and/or displayed.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ahmed Hazem Mohamed Rashid El-Mahdy, Hisham ElShishiny
  • Patent number: 8272041
    Abstract: Generally speaking, systems, methods and media for implementing a firewall control system responsive to process interrogations are disclosed. Embodiments of a method may include receiving a data request at a firewall where the data request is associated with a program and determining whether a process rule exists for the associated program, where the process rule includes a condition to be satisfied for a process of the user computer system. Embodiments may also include, in response to determining that a process rule does exist, determining a method for evaluating a status of the process and determining a current status of the process. Embodiments may also include determining whether the process rule is satisfied based on the current status of the process and using the determined evaluation method. Embodiments may also include, in response to determining whether the condition of the process rule is satisfied, performing one or more firewall actions.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: September 18, 2012
    Assignee: International Business Machines Corporation
    Inventors: Rick A. Hamilton, II, Brian M. O'Connell, John R. Pavesi, Keith R. Walker
  • Patent number: 8246392
    Abstract: An electrical cable connector comprising an electrically conductive central body, an outer sleeve rotatably coupled to the central body, and a tubular cam member disposed between the outer sleeve and the central body. When the outer sleeve is rotated around the central body from a first rotational position to a second rotational position, the tubular cam member is displaced from a first axial position to a second axial position, thereby causing a radial camming region in an axial through bore of the tubular cam member to displace fingers of the electrically conductive central body radially inwardly. In that manner, when the connector is plugged into a port or jack comprising a cylindrical body that is at least partially enclosed by the fingers of the central body of the connector, the fingers clamp onto the body of the port, thereby securing the connector to the port.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: August 21, 2012
    Assignee: John Mezzalingua Associates, Inc.
    Inventor: Jeremy Amidon
  • Patent number: 8182978
    Abstract: Compositions characterized by the presence of an aqueous base-soluble polymer having aromatic moieties and aliphatic alcohol moieties have been found which are especially useful as developable bottom antireflective coatings in 193 nm lithographic processes. The compositions enable improved lithographic processes which are especially useful in the context of subsequent ion implantation or other similar processes where avoidance of aggressive antireflective coating removal techniques is desired.
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wu-Song Huang, Libor Vyklicky, Pushkara Rao Varanasi
  • Patent number: 7937584
    Abstract: A method and system for key certification in a public key infrastructure. The infrastructure has a network formed of a plurality of nodes. Each node has a private and public key pair. The nodes are either or both a certifying node and a certified node. A certifying node provides a digital certificate referring to the public key of a certified node. The digital certificate is signed by the private key of the certifying node. The method includes providing a root public key for a user, the root public key being at any node in the network chosen by the user, and providing a chain of digital certificates from the node with the root public key across the node network to any other node.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Peter Roy Dare, John Owlett
  • Patent number: 7894608
    Abstract: A secure approach for sending a original message from a sender to a receiver. The sender may encrypt the original message by performing an XOR (or XNOR) operation of the original message and a first random message (same size as original message) on a bit by basis to generate a second message. The receiver may also perform an XOR of the second message with a locally generated second random message. The resulting message is sent to the sender system. The sender system may again perform XOR operation of the received message and the first random message, and send the resulting message to receiver. The receiver may perform XOR operation on the received output to generate the original message sent by the sender. Other technologies such as digital signatures and key pairs (public key infrastructure) may be used in each communication between the sender and receiver to further enhance security.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventor: Devi Prashanth
  • Patent number: 7895487
    Abstract: A structure and method for optimzing scan chain fail disgnosis. First, logic paths from target latches in a target scan chain to observation latches in at least one other observation scan chain are identified. Then, the locations of the observation latches within the other scan chains are optimized.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: February 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Leendert M. Huisman, Leah M. Pastel
  • Patent number: 7779140
    Abstract: A method and system for switching media streams of a video in a client system. The media streams are made available to the client system by a content providing system. A first media stream received from the content providing system is played in a SHOW mode in the client system. A command is received from a control system to execute a procedure for deciding whether to switch from playing the first media stream to playing a second media stream which has a different media stream bandwidth than the first media stream. The executed procedure decides to make the switch. The switch is made to playing the second media stream in the SHOW mode as the second media stream is being received from the content providing system in response having been requested from the content providing system. The switching preserves content continuity of the video.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: August 17, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey David Amsterdam, Christopher Eythan Holladay, Ryan Lynch Whitman
  • Patent number: 7772083
    Abstract: An electrical structure and method of forming. The method includes providing a semiconductor structure comprising a semiconductor substrate, a buried oxide layer (BOX) formed over the semiconductor substrate, and a silicon on insulator layer (SOI) formed over and in contact with the BOX layer. The SOI layer comprises shallow trench isolation (STI) structures formed between electrical devices. A first photoresist layer is formed over the STI structures and the electrical devices. Portions of said first photoresist layer, portions of the STI structures, and portions of the BOX layer are removed resulting in formed trenches. Ion implants are formed within portions of the semiconductor substrate. Remaining portions of the first photoresist layer are removed. A dielectric layer is formed over the electrical devices and within the trenches. A second photoresist layer is formed over the dielectric layer. Portions of the second photoresist layer are removed.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Alan Bernard Botula, Michael Lawrence Gautsch, Alvin Jose Joseph, Max Gerald Levy, James Albert Slinkman
  • Patent number: 7709967
    Abstract: An interconnect structure, method of fabricating the interconnect structure and method of designing the interconnect structure for use in semiconductor devices. The interconnect structure includes a damascene metal wire having a pattern of dielectric filled holes.
    Type: Grant
    Filed: August 13, 2007
    Date of Patent: May 4, 2010
    Assignee: International Business Machines Corporation
    Inventors: Timothy G. Dunham, Ezra D. B. Hall, Howard S. Landis, Mark A. Lavin, William C. Leipold
  • Patent number: 7529714
    Abstract: A method for managing a cost of ownership of a portfolio of N software applications (N?2). A regression function is identified for each application. Each regression function expresses an approximate cost of ownership of the applications in terms of parameters and coefficients. J applications A1, A2, . . . , AJ are selected from the N applications such that a remaining N?J applications are unselected (J<N). The coefficients for the N?J unselected applications constitute a subset of the coefficients for the J selected applications. Fj represents the approximate cost of ownership of the application Aj for j=1, 2, . . . , J. An actual cost of ownership Gj of application Aj for j=1, 2, . . . , J is provided. The coefficients for the J selected applications are determined so as to minimize a function H=?j Wj|Fj?Gj|P(P>0). ?j represents a summation over j from j=1 to j=J. Wj are predetermined weights.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: May 5, 2009
    Assignee: International Business Machines Corporation
    Inventors: Dmitrii Andreev, Paul G. Greenstein, Gregory Vilshansky
  • Patent number: 7487107
    Abstract: A system and a method for selecting potential purchasers from a historical collection of confirmed purchasers. The method allows definition of a set of purchasing variables in relation to the confirmed purchasers, and computation of both a plurality of re-purchasing ratios and a plurality of purchasing amounts using the set of purchasing variables. Potential purchasing amounts are generated by combining the previous results.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jean-Louis Blanchard, Hammou Messatfa, Stephane Lorin, Christelle Pavillon
  • Patent number: 7436006
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: October 14, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Huilong Zhu
  • Patent number: 7434129
    Abstract: An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: October 7, 2008
    Assignee: International Business Machines Corporation
    Inventors: Leonard O. Farnsworth, III, Michael Z. Felske, Pamela S. Gillia, Benjamin P. Lynch, Michael R. Ouellette, Thomas St. Pierre, Tad J. Wilder, Carl F. Barnhart
  • Patent number: 7402890
    Abstract: A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: David S. Collins, Hanyi Ding, Kai Di Feng, Zhong-Xiang He, Xuefeng Liu
  • Patent number: 7399581
    Abstract: A composition that includes functionalized polyhedral oligomeric silsesquioxanes derivatives of the formulas TmR3 where m is equal to 8, 10 or 12 and QnMnR1,R2,R3 where n is equal to 8, 10 or 12 are provided. The functional groups include aqueous base soluble moieties. Mixtures of the functionalized polyhedral oligomeric silsesquioxanes derivatives are highly suitable as a topcoat for photoresist in photolithography and immersion photolithography applications.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Robert David Allen, Ratnam Sooriyakumaran, Linda Karin Sundberg
  • Patent number: 7386771
    Abstract: A memory sub-system and a method for operating the same. The memory sub-system includes (a) a main memory, (b) an ECC circuit, (c) a hard fail identifier circuit, (d) a repair circuit, (e) a redundant memory, and (f) a threshold setting circuit. The ECC circuit is capable of (i) detecting a first bit fail, (ii) sending an error flag signal to the hard fail identifier circuit, (iii) sending a first location address, a first bit location of the first bit fail, and a repaired data from the first location address to the hard fail identifier circuit. The hard fail identifier circuit is capable of (i) determining the number of times of failure occurring at the first bit fail, (ii) determining whether the number of times of failure is equal to a predetermined threshold value, and (iii) if so, sending a threshold reached signal.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: June 10, 2008
    Assignee: International Business Machines Corporation
    Inventor: Stephen Gerard Shuma
  • Patent number: D604113
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: November 17, 2009
    Inventor: Nely Cristina Braidotti
  • Patent number: D644210
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: August 30, 2011
    Assignee: Hannspree Inc.
    Inventor: Yi-Chung Chiu
  • Patent number: D646831
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 11, 2011
    Assignee: Vas Lighting Co., Limited
    Inventor: Dezhi Pan