Abstract: A method, system and computer program product for dynamically composing processor cores to form logical processors. Processor cores are composable in that the processor cores are dynamically allocated to form a logical processor to handle a change in the operating status. Once a change in the operating status is detected, a mechanism may be triggered to recompose one or more processor cores into a logical processor to handle the change in the operating status. An analysis may be performed as to how one or more processor cores should be recomposed to handle the change in the operating status. After the analysis, the one or more processor cores are recomposed into the logical processor to handle the change in the operating status. By dynamically allocating the processor cores to handle the change in the operating status, performance and power efficiency is improved.

Abstract: Method and apparatus enabling a computing system to deter or thwart unauthorized boot-up from peripheral devices are disclosed herein. In various embodiments, a monitoring module and a managing module are employed cooperating with each other to authorize users in booting up the computing system from peripheral devices.

Abstract: In a wireless network in which the base station has full duplex capability (can transmit on the downlink channel and simultaneously receive on the uplink channel), but the mobile stations have only half duplex capability (each can transmit on the uplink channel and receive on the downlink channel, but not simultaneously), the base station may transmit duplicate copies of multicast data in two or more frames. Some of the addressed mobile station may be scheduled to receive the first frame and transmit during the second frame, while the other addressed mobile stations may be scheduled to transmit during the first frame and receive the second frame.

Abstract: A spectral filter comprises a planar optical waveguide having at least one set of diffractive elements. The waveguide confines in one transverse dimension an optical signal propagating in two other dimensions therein. The waveguide supports multiple transverse modes. Each diffractive element set routes, between input and output ports, a diffracted portion of the optical signal propagating in the planar waveguide and diffracted by the diffractive elements. The diffracted portion of the optical signal reaches the output port as a superposition of multiple transverse modes. A multimode optical source may launch the optical signal into the planar waveguide, through the corresponding input optical port, as a superposition of multiple transverse modes. A multimode output waveguide may receive, through the output port, the diffracted portion of the optical signal. Multiple diffractive element sets may route corresponding diffracted portions of optical signal between one or more corresponding input and output ports.

Abstract: Embodiments of the present invention include but are not limited to methods and systems for optical coherence imaging. A method for optical coherence imaging may comprise scanning a sample with an incident beam from a light source; detecting one or more spectral interference signals from the sample; modulating the one or more spectral interference signals by a linear translation of a reference mirror while scanning the sample in a cross-sectional direction; and obtaining at least one image of the sample from the modulated one or more spectral interference signals, the at least one image including a selected one of a full range structural image of the sample and a separated structure/flow image of the sample.

Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.

Abstract: Techniques for non-invasive, post-silicon characterization of signal propagation delay/timing of devices in an integrated circuit (IC) are generally disclosed. A system of equations may be developed based on a plurality of sensitizable signal paths (SSPs) of the IC for characterizing signal propagation delay or timing of devices within the SSPs. Input Vectors (IVs) may be selected and consecutively applied at one or more input sequential element devices of the IC associated with the SSPs with to produce corresponding output values at one or more output sequential element devices of the IC associated with the SSPs. Various pre-processing and post-processing techniques may be practiced to further improve accuracy of solution of the equations to enable efficient determination of solutions. Example techniques may include variable splitting, device clustering, IV and equation selection, and boosting, among others. Other aspects may also be disclosed and claimed.

Abstract: Techniques are generally described for designing an integrated circuit (IC). In various embodiments, the techniques include designing, at a functional specification level, N-variants of a particular circuit. The various embodiments may then implement the designed N-variants as hardware in the IC. Additional variants and embodiments may also be disclosed.

Abstract: Systems for facilitating conversion between reciprocating linear motion and rotational motion include a continuous undulating track circumscribing a circular profile and generally defining a cylindrical volume having a central axis; a reciprocator that is configured to linearly reciprocate along the central axis; a converter coupled to the reciprocator to reciprocate with it, configured to rotate about the central axis, and engaged with the undulating track; and a rotator engaged with the converter and configured to rotate about the central axis with the converter but not to linearly reciprocate along the central axis.

Abstract: An H-tree is formed in a conducting layer over a base array of a structured ASIC, the H-tree being a predefined constraint imposed on ad hoc circuit designs adapted to make use of a base array and H-tree. The endpoints of an H-tree can be formed at or near sequential elements. When an H-tree is used as part of a clock structure, clock skew to sequential elements and consumption of routing resources for forming a clock structure can be minimized. When a pulse generator is coupled to an H-tree, at least one flip-flop of a plurality of flip-flops can be emulated with an individual latch, thereby increasing effective flip-flop density.

Abstract: A home-networking gateway may provide a service to a device on a home network by transparently accessing (or spoofing) a capability of a different device on the home network. The device capabilities may be automatically detected and used. A home-networking gateway also may transparently provide a service from a host system to a device on a home network by accessing a service on a host system.