Abstract: Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate. This method includes depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate. The seed layer is deposited to a thickness of less than 15 nanometers (nm). A photolithography technique is used to define a number of via holes above the seed layer. In one embodiment, using a photolithography technique includes forming a patterned photoresist layer to define the number of via holes above the seed layer. A layer of copper is deposited over the seed layer using electroless plating filling the number of via holes to a top surface of the patterned photoresist layer.

Abstract: A capacitor for use in integrated circuits comprises a layer of conductive material. The layer of conductive material including at least a first portion and a second portion, wherein the first portion and the second portion are arranged in a predetermined pattern relative to one another to provide a maximum amount of capacitance per semiconductor die area.

Abstract: To reduce cost and improve accuracy, the inventors devised systems, methods, and software to aid classification of text, such as headnotes and other documents, to target classes in a target classification system. For example, one system computes composite scores based on: similarity of input text to text assigned to each of the target classes; similarity of non-target classes assigned to the input text and target classes; probability of a target class given a set of one or more non-target classes assigned to the input text; and/or probability of the input text given text assigned to the target classes. The exemplary system then evaluates the composite scores using class-specific decision criteria, such as thresholds, ultimately assigning or recommending assignment of the input text to one or more of the target classes. The exemplary system is particularly suitable for classification systems having thousands of classes.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: An integrated circuit with a number of optical waveguides that are formed in high aspect ratio holes. The high aspect ratio holes extend through a semiconductor wafer. The optical waveguides include a highly reflective material that is deposited so as to line an inner surface of the high aspect ratio holes which may be filled with air or a material with an index of refraction that is greater than 1. These metal confined waveguides are used to transmit signals between functional circuits on the semiconductor wafer and functional circuits on the back of the wafer or beneath the wafer.

Abstract: Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Abstract: A typical integrated-circuit fabrication requires interconnecting millions of microscopic transistors and resistors with aluminum wires. Yet, aluminum wires have greater electrical resistance and are less reliable than copper wires. Unfortunately, current techniques for making copper wires are time-consuming and inefficient. Accordingly, the invention provides a method of making wires or interconnects from copper or other metals. One embodiment entails forming a first diffusion barrier inside a trench using ionized-magnetron sputtering for better conformal coating of the trench, and a second diffusion barrier outside the trench using jet-vapor deposition. The jet-vapor deposition has an acute angle of incidence which prevents deposition within the trench and thus eliminates conventional etching steps that would otherwise be required to leave the trench free of this material. After formation of the two diffusion barriers, the trench is filled with metal and annealed.

Abstract: Embodiments of the present invention include an interface circuit to put an integrated circuit into a test mode and a decoder to decode one or more commands provided to the integrated circuit. The decoder includes sub-circuits, and each sub-circuit has a number of transistors coupled in series. The transistors coupled in series have control gates coupled to a clock signal or one of several inverted or non-inverted command signals representing a command. The control gates in each sub-circuit are coupled such that a unique pattern of the clock signal and the command signals will switch on all of the transistors to decode the command. Each sub-circuit is capable of decoding a single command. The sub-circuits have ratioed logic with more n-channel transistors than p-channel transistors. The decoder may be fabricated with a flexible placement of vias.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A method to prepare epidermal stem cells, and isolated epidermal stem cells, is provided. Also provided are methods of using epidermal stem cells, e.g., for cell based therapies.

Abstract: A power management system for an implantable device is disclosed. One application is an implantable cardioverter/defibrillator. Charging circuits for implantable cardioverter/defibrillators require relatively large currents from the power supply. The present power management system provides extended device operation and reduced charge cycle time. The present system monitors both current and voltage drawn from the power supply to prevent a loss of system voltage. Elective replacement indication is performed using charging information provided by the present power management system.

Abstract: An integrated circuit operable in a test mode and a normal operating mode, which includes an improved test mode switch. In the test mode of preferred embodiments in which the circuit is an integrated memory chip, the test mode switch is closed so as to connect an input/output (I/O) pad directly with a selected memory cell (so a current/voltage characterization of the cell can be obtained). In the normal operating mode of these embodiments, the test mode switch is open and it isolates the I/O pad from direct connection with the selected cell even under the condition that a transistor of the test mode switch undesirably becomes conductive (e.g., due to low voltage on the I/O pad, inductive coupling, or the like).

Abstract: A video system is described which creates a virtual shadow of a foreground object filmed in front of a blue screen with a main video camera. The virtual shadow is created using a second video camera located as a virtual light source. Images from both cameras are processed by a chroma keyer to separate the foreground object. The video image from the second camera is processed to create the virtual shadow and both video images are combined with background image. Object location and actor prompting systems are described.