Abstract: A system, computer-readable storage medium including instructions, and a computer-implemented method for obtaining votes for participants in a television program are described, in which code for a game is transmitted to a computer system, where the game includes an in-game voting module that allows a player of the game to cast votes for participants in a television program. At least one vote for at least one participant in the television program is received from the in-game voting module. A database including vote counts for the participants in the television program is updated based on the at least one vote for the at least one participant.

Abstract: A telemetry system is presented for enabling radio-frequency (RF) communications between implantable medical devices and an external device in a manner which increases the effective range over which such communications may take place. Devices are configured to relay communications from one device to another.

Abstract: A method and a system is provided to process data. For example, the method and system may be used to store (e.g., archive) documents. In an embodiment, the method comprises receiving a quantum of data and creating n data pieces of size s from the quantum of data. The method may comprise generating k random numbers of size s, wherein k defines a minimum number of processed data pieces required to reconstruct the quantum of data, and performing polynomial arithmetic modulo prime on the n data pieces. The polynomial arithmetic may utilize polynomial of order k and the prime may be selected based on a bit processing capability of a processor used to process the data. The prime may be 28+1 when the bit processing capability of a processor is 16 bits and 216+1 when the bit processing capability of a processor is 32 bits.

Abstract: This invention relates to control techniques and controllers for resonant discontinuous forward power converters (RDFCs). A controller for a resonant discontinuous forward converter (RDFC), said converter including a transformer with primary and secondary matched polarity windings and a switch to, in operation, cyclically switch DC power to said primary winding of said transformer, said converter further having a DC output coupled to said secondary winding of said converter, said controller having a primary sense input to sense a primary winding signal, said primary winding signal representing a voltage across said primary winding or across an additional winding coupled to said primary winding, and wherein said controller is configured to switch on said switch in response to detection of a reduction in a rate of change of said primary winding signal below a threshold, adjacent a substantially minimum value in an operational cycle of said sensed primary winding signal to convey power to said DC output.

Abstract: A deformable screen for a window assembly including a sash movably coupled to a frame. The sash is moveable in a substantially horizontal direction relative to the frame. The deformable screen is coupled to the sash and includes at least one engagement portion slidably engaged against the frame. A spring member is coupled to the engagement portion and applies a restoring force to the engagement portion to seal it against the frame. In one option, the spring member includes a foam membrane. A method for making a screen assembly includes providing a frame and a sash disposed within the frame. A spring member is coupled around the sash and at least one engagement portion is coupled to the spring member. The engagement portion extends between the spring member and the window frame, in one option. In another option, the at least one engagement portion is slidably engaged against the frame.

Abstract: Flip chip packages formed at a wafer level on semiconductor wafers for electronic systems provide convenient prepackaging. The package, in one embodiment, includes an adhesive layer applied to an active side of the wafer. The adhesive layer has openings to permit access to the conductive pads on each die. A conductive material substantially fills the openings. A pre-packaged die diced from the semiconductor wafer is mounted to a support wherein the conductive material effects electrical interconnection between the conductive pads on the die and receiving conductors on the support. The pre-packaged die can be coupled to a processor for an electronic system. To provide greater mounting densities, two or more dice may be coupled with the adhesive layer providing a covering for the two or more dice. The prepackaged chip with two or more dice may be coupled to a processor reducing the volume needed in an electronic system.

Abstract: The present invention relates to a method of suppressing bone marrow (BM) and treating conditions that arise in or near bone such as cancer, myeloproliferative diseases, autoimmune diseases, infectious diseases, metabolic diseases or genetic diseases, with compositions having as their active ingredient a radionuclide complexed with a chelating agent such as macrocyclic aminophosphonic acid.

Abstract: Circuitry for testing a power-on-reset circuit in an integrated circuit includes a high-voltage detector coupled to a first I/O pad of the integrated circuit. A power-on-reset circuit in the integrated circuit has an output coupled to a driver circuit that is powered by the high-voltage. A second I/O pad of the integrated circuit is coupled to the output of the driver circuit. The driver circuit may be enabled by a signal provided on a third I/O pad of the integrated circuit.

Abstract: A circuit, with applications to phase-locked loops and frequency synthesis, where a divider circuit shuffles between dividing the output of a voltage-controlled oscillator by N or N+1, where N is an integer, and where a phase frequency detector provides three logic signals to a charge pump so that one of three values of current may be sourced to a loop filter, with the result that the circuit behaves as a conventional phase-lockup loop fictitious divider circuit that is capable of dividing the output of the voltage-controlled oscillator by a non-integral value.

Abstract: Improved methods for providing fault tolerance in a distributed computer system utilize an explicit, delayed acknowledgement message protocol to send an acknowledgement message to a workflow-requesting entity, such as a load manager and/or a requesting client, only upon completion of a workflow. The system includes workflow engines operating as a distributed queue group to load-balance processing requests from clients. The system also has a certified messaging capability that guarantees delivery of any message sent by a certified message sender by maintaining a persistent record of the message until an acknowledgement message is received back from the certified message receiver. In the event a hardware or software failure occurs during a workflow execution, the workflow is reassigned to a different workflow engine. Improved fault-tolerant computers and computer networks are also described.

Abstract: In a wireless local area network (WLAN) that includes high-throughput communication devices with multiple antennas and legacy communication devices with single antennas, training tones are transmitted over a plurality of spatial channels during a first portion of an orthogonal frequency division multiplexed (OFDM) packet-training preamble. The training tones are interspersed among subcarrier frequencies of the spatial channels. The training tones are retransmitted during a second portion of the packet-training preamble. The training tones are shifted among the subcarrier frequencies of the spatial channels during the retransmission allowing a high-throughput receiving station to perform a channel estimation on different subcarrier frequencies of the spatial channels. The legacy communication devices may receive and process the training tones and may set their network allocation vector to refrain from communicating during a subsequent interval.

Abstract: A memory array has memory elements of identical topology or footprint arranged in rows and columns. Some of the memory elements are EEPROM cells and other memory elements are read only memory cells but all are made using a mask set having the same length and width dimensions. In the mask set for EEPROMs a principal mask is used for formation of a depletion implant. In the case of one type of read-only memory element, this mask is mainly blocked, leading to formation of a transistor with a non-conductive channel between source and drain. In the case of another read only memory element, the same mask is unblocked, leading to formation of a transistor with a highly conductive or almost shorted channel between source and drain. These two read only memory elements are designated as logic one and logic zero. By having rows of read-only memory elements with rows of EEPROMs on the same chip, a more versatile memory array chip may be built without sacrificing chip space.

Abstract: A method of testing, polling and trimming memory pages in different memory banks simultaneously is presented, using a cache memory located in each one of the memory banks. The cache memory is at least as large as the individual memory pages and is used to record the programming voltage required to obtain the specified programming speed as well as the location of defective memory elements. A local on chip state machine may be used to accelerate the programming rate, and there may be a state machine per memory bank. With such an arrangement, the amount of testing time at wafer probe and final packaged device test may be reduced up to 40%, depending upon the number of memory pages tested in parallel.