Patents Represented by Attorney Schwegman Lundberg Woessner & Kluth
  • Patent number: 7262482
    Abstract: The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7261896
    Abstract: The present invention provides a method for reducing stroke-related tissue damage by treating a mammal with E-selectin. Preferably, this treatment induces E-selectin tolerance in the mammal. Another aspect of the invention is a method for inducing E-selectin tolerance in a mammal through intranasal administration of E-selectin, preferably including booster administrations. The present methods are especially adapted for use in patients at increased risk of stroke or who may become at increased risk of stroke.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: August 28, 2007
    Assignee: United States of America as represented by the Secretary of the Department of Health and Human Services National Institutes of Health
    Inventors: John M. Hallenbeck, Hidetaka Takeda, Maria Spatz
  • Patent number: 7262077
    Abstract: A method of packaging a die includes attaching the die to a substrate; underfilling the space between the die and the substrate with a first material, and placing a second material in contact with at least a portion of the die and the substrate after underfilling the space between the die and substrate with the first material. A system includes a semiconductor package having a substrate, a die attached to the substrate, an underfill material positioned between the die and the substrate, and a molding material in contact with at least a portion of the substrate and the die. A heat sink is also in thermal contact with the semiconductor package.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Yin Men Lai, Choong Kooi Chee, Edward Then, Cheong Huat Ng, Mun Fai Low
  • Patent number: 7263692
    Abstract: A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming sparse array matrix source code and software-pipelining the transformed source code to reduce recurrence initiation interval, decrease run time, and enhance performance.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Kalyan Muthukumar, Gautam Doshi, Dattatraya Kulkarni
  • Patent number: 7262492
    Abstract: Some embodiments relate to a semiconducting device that includes a substrate, a die and an interconnect device. The die and interconnect device are attached to an upper surface of the substrate. The semiconducting device further includes a first wire that is bonded to the substrate and to the interconnect device and a second wire that is bonded to the interconnect device and to the die. Other example embodiments include a stack of dice that has a bottom die attached to the upper surface of the substrate and a top die stacked onto the other dice in the stack of dice. The interconnect device is attached to an upper surface of any die in the stack of dice such that a first wire is bonded to the substrate and to the interconnect device and a second wire is bonded to the interconnect device and to the top die.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: August 28, 2007
    Assignee: Intel Corporation
    Inventors: Ruel B. Pieda, Carmelito M. Libay, Joan Rey V. Buot
  • Patent number: 7263718
    Abstract: An inventive security framework for supporting kernel-based hypervisors within a computer system. The security framework includes a security master, one or more security modules and a security manager, wherein the security master and security modules execute in kernel space.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: August 28, 2007
    Assignee: Secure Computing Corporation
    Inventors: Richard O'Brien, Raymond Lu, Terrence Mitchem, Spencer Minear
  • Patent number: 7261928
    Abstract: A package coating is processed by applying a plurality of aqueous mixtures over a substrate. The aqueous mixtures each include a combination of pigments and binders. A packaging article is also disclosed that is made from the package coating on a substrate. Additionally, a packaging system is included that contains commercial product.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: August 28, 2007
    Assignee: Potlatch Corporation
    Inventors: Melvin Jokela, Cathy Kortesmaki, Ann Williams
  • Patent number: 7262130
    Abstract: Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, copper typically requires use of a diffusion barrier to prevent it from contaminating other parts of an integrated circuit. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some advantages of using copper. Moreover, conventional methods of forming the copper wiring are costly and time consuming. Accordingly, the inventors devised one or more exemplary methods for making integrated-circuit wiring from materials, such as copper-, silver-, and gold-based metals.
    Type: Grant
    Filed: January 18, 2000
    Date of Patent: August 28, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7262219
    Abstract: Disclosed are formulations of gamma-hydroxybutyrate in an aqueous medium that are resistant to microbial growth. Also disclosed are formulations of gamma-hydroxybutyrate that are also resistant to the conversion into GBL. Disclosed are methods to treat sleep disorders, including narcolepsy, with these stable formulations of GHB. The present invention also provides methods to treat alcohol and opiate withdrawal, reduced levels of growth hormone, increased intracranial pressure, and physical pain in a patient.
    Type: Grant
    Filed: May 7, 2004
    Date of Patent: August 28, 2007
    Assignee: Orphan Medical, Inc.
    Inventors: Harry Cook, Martha Hamilton, Douglas Danielson, Colette Goderstad, Dayton Reardan
  • Patent number: 7259601
    Abstract: A clock synchronization circuit (200, FIG. 2) includes a signal selector (202), phase detector (204), and delay line (206). The signal selector compares an external clock signal (220) and a feedback signal (222) to evaluate the jitter present in the external clock signal. When the jitter falls within an acceptable range, the circuit operates in DLL mode. In DLL mode, the external clock signal is provided to the delay line, and the delayed external signal is output (224) from the circuit. If the jitter falls outside the acceptable range and the circuit is locked, the circuit is switched to PLL mode. In PLL mode, a clock signal based on the feedback signal is provided to the delay line, and the delayed feedback signal is output from the circuit. The PLL mode is only allowed to operate briefly before switching the circuit back into DLL mode.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Oliver F. Zarate, Tyler J. Gomm
  • Patent number: 7259434
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Also shown is a gate oxide with a conduction band offset in a range of approximately 5.16 eV to 7.8 eV. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: August 21, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7260595
    Abstract: Logic circuit for generating carry or sum bit output by combining binary inputs, includes bit level carry generate and propagate function logic receiving binary inputs and generating bit level carry generate/propagate function bits for binary inputs by respectively logically AND and OR combining respective bits of binary inputs; logic generating high output if a carry is generated out of a first group of most significant bits of binary input or if carry propagate function bits for the most significant bits are all high; logic for receiving bit level carry generate and propagate function bits for binary inputs to generate high output if any of carry generate function bits for the most significant bits are high or if carry is generated out of another group of least significant bits of binary input; and logic for generating the carry or sum bit output by combining outputs of the two logics.
    Type: Grant
    Filed: November 14, 2003
    Date of Patent: August 21, 2007
    Assignee: Arithmatica Limited
    Inventors: Sunil Talwar, Robert Jackson
  • Patent number: 7260362
    Abstract: During formation of an ad hoc group, the transmit power level of a user device within a wireless communication network is reduced. Potential group members are thus identified within an immediate vicinity of the user device.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventor: Daniel A. Teibel
  • Patent number: 7260736
    Abstract: A device and method to detect and correct for clock duty cycle skew in a high performance microprocessor having a very high frequency clock. The device includes a delay chain circuit to delay the clock signal and to determine the presence of clock duty cycle skew. The device uses simple latches, flops, and phase-detectors to compare and identify the nature of the clock duty cycle skew. Simple logic is employed to measure and determine the amount and direction of de-skew to apply to the clock signal. After the de-skew operation, the clock duty cycle cycles used to control the execution of the microprocessor are of a more uniform time duration.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventor: Binglong Zhang
  • Patent number: 7260427
    Abstract: Systems and methods for determining the coronary sinus vein branch location of a left ventricle electrode are disclosed. The systems and methods involve detecting the occurrence of electrical events within the patient's heart including sensing one or more of the electrical events with the electrode and then analyzing the electrical events to determine the electrode's position. The determination of electrode position may be used to automatically adjust operating parameters of a VRT device. Furthermore, the determination of electrode position may be made in real-time during installation of the electrode and a visual indication of the electrode position may be provided on a display screen.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: August 21, 2007
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Yinghong Yu, Jiang Ding, Jeng Mah, Julio Spinelli
  • Patent number: 7260429
    Abstract: A cardiac rhythm management system provides a phonocardiographic image indicative of a heart's mechanical events related to hemodynamic performance. The phonocardiographic image includes a stack of acoustic sensor signal segments representing multiple cardiac cycles. Each acoustic sensor signal segment includes heart sounds indicative of the heart's mechanical events and representations of the heart's electrical events. The stack of acoustic sensor signal segments are aligned by a selected type of the heart's mechanical or electrical events and are grouped by a cardiac timing parameter for presentation.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: August 21, 2007
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Krzysztof Z. Siejko, Gerrard M. Carlson, William C. Lincoln, Qingsheng Zhu
  • Patent number: 7260659
    Abstract: An apparatus and a system, as well as a method and article, may operate to include repeating first data to provide first repeated data and deleting second repeated data to provide second data according to a programmed standard included in a first apparatus and selected from a plurality of reprogrammable standards.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: August 21, 2007
    Assignee: Intel Corporation
    Inventors: Inching Chen, Anthony L. Chun
  • Patent number: 7258242
    Abstract: The present invention relates to a mobile crane boom having a self-sufficient energy supply arranged on it for supplying hydraulic energy to at least one hydraulic load arranged on the mobile crane boom. The supply of the hydraulic load arranged on the mobile crane boom is therefore not carried out by means of a hydraulic unit arranged on the revolving superstructure of the crane, which provides the hydraulic energy to each hydraulic load via hoses, but by means of a hydraulic unit which is arranged in the upper reaches of the mobile crane boom or in the area of the linkage of any second boom section. By arranging the hydraulic unit directly on the boom, the hoses normally required for supplying the hydraulic loads can be eliminated.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: August 21, 2007
    Assignee: Terex-Demag GmbH & Co. KG
    Inventors: Michael Irsch, Bernd Backes
  • Patent number: 7260431
    Abstract: A method and device for delivering ventricular resynchronization pacing therapy in conjunction with electrical stimulation of nerves which alter the activity of the autonomic nervous system is disclosed. Such therapies may be delivered by an implantable device and are useful in preventing the deleterious ventricular remodeling which occurs as a result of a heart attack or heart failure. The device may perform an assessment of cardiac function in order to individually modulate the delivery of the two types of therapy.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 21, 2007
    Assignee: Cardiac Pacemakers, Inc.
    Inventors: Imad Libbus, Bruce H. KenKnight, Julia Moffitt, Yatheendhar D. Manicka
  • Patent number: 7258870
    Abstract: The present invention relates to a method of increasing the live weight of poultry through the administration of a plasma product to the poultry through the animals' feed and/or water. The product is effective in increasing the live weight of poultry. The product is also surprisingly effective in increasing the yield of white meat to the detriment of dark meat.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: August 21, 2007
    Assignee: The Lauridsen Group Incorporated
    Inventors: Joy M. Campbell, Louis E. Russell, Barton S. Borg, James D. Quigley, III