Abstract: An apparatus, program product and method integrate virus checking functionality into a computer database search environment to assist in protecting a user computer from contracting a computer virus when accessing search results. The generation of a display representation of a result set generated in response to a search request may be based at least in part upon virus status information associated with at least a portion of a plurality of result records identified in the generated result set. Moreover, an apparatus, program product, and method configure a first computer to receive virus status information generated by a plurality of computers, with such received virus status information stored in a virus database that is accessible by the first computer.

Abstract: In a shared memory system, a plurality of requesters issue requests for particular memory addresses over a system bus. Requests, if denied, are later reissued after a controlled reissue delay. The reissue delay for a particular request is controllably varied in response to the number of requests being issued by requesters other than that which issued the request. Typically, the number of requests issued by other requesters for a common memory address as the particular request is tracked, and the reissue delay is controllably increased as the number of such requests increases. As such, the frequency that requests for highly contended memory addresses (which are more likely to be denied) is decreased relative to requests for less contended addresses, thereby freeing bandwidth on the system bus for requests that are more likely to be granted.

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit.

Abstract: A memory controller circuit arrangement and method utilize a tuning circuit that dynamically controls the timing of memory control operations, rather than simply relying on fixed timing parameters that are either hardwired or initialized upon startup of a memory controller. Dynamic control over the timing of memory control operations typically incorporates memory test control logic that verifies whether or not a memory storage device will reliably operate using the dynamically-selected values of given timing parameters. Then, based upon the results of such testing, such dynamically-selected values are selectively updated and retested until optimum values are found. The dynamically-selected values may be used to set one or more programmable registers, each of which may in turn be used to control the operation of a programmable delay counter that enables a state transition in a state machine logic circuit to initiate performance of a memory control operation by the logic circuit.

Abstract: A computer system and method concurrently present multiple development threads represented by a collection of chronologically-arranged information. An abstraction stack is used to access a body of knowledge stratified into a plurality of levels of abstraction and including a plurality of information elements associated with the plurality of levels of abstraction and organized generally chronologically in the body of knowledge. The abstraction stack concurrently displays first and second representations of a common portion of the body of knowledge, with the first and second representations respectively displaying first and second information elements respectively associated with first and second levels of abstraction. The first and second levels of abstraction are respectively associated with separate development threads such that such threads are concurrently presented to a user.

Abstract: An apparatus, program product, and method of testing a silicon-on-insulator (SOI) static random access memory (SRAM) introduce switching history effects to a memory cell under test to stress the memory cell such that a reliable determination of stability may be made. It has been found that the worst case scenario for memory cell stability typically occurs immediately after a memory cell is switched to one state after the memory cell has been maintained in the other, opposite state for a period of time sufficient to introduce switching history effects. As such, a testing process may be configured to maintain a memory cell in a particular state for a period of time sufficient to introduce switching history effects, whereby the memory cell may be adequately stressed during the testing process to highlight any stability problems by setting the memory cell to an opposite state, and then shortly thereafter disturbing the memory cell, e.g.

Abstract: A computer system and method of controlling a computer system integrate the display of a user interface control from which a user supplies input to a computer system with the display of multiple representations of instructional material related to how to operate the control. Displayed representations of first and second sets of instructional material may be concurrently or selectively integrated with a displayed representation of the user interface control. When multiple sets of instructional material are concurrently displayed, the user interface control may be actuated in response to user input supplied to multiple displayed representations of the user interface control. Moreover, when multiple sets of instructional material are selectively displayed, different sets of such material may replace other sets in response to user input.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize a data buffer with a priority-based data storage capability to handle incoming data from a plurality of available data sources. With such a capability, different relative priority levels are assigned to data associated with different data sources. Such priority levels are then used by control logic coupled to the buffer to control whether or not incoming data is stored (or optionally discarded) in the buffer. In particular, the relative priority of incoming data is compared with that associated with data currently stored in the buffer, with the incoming data being stored in the buffer only when its relative priority exceeds that of the currently-stored data.

Abstract: An apparatus, program product and method of managing computer resources each facilitate concurrent maintenance operations by automatically re-associating existing resources in a computer, when suitable, with appropriate hardware devices installed into the computer after a concurrent maintenance operation has been performed. An existing resource is re-associated with an installed hardware device by updating at least one of a device identifier and a location identifier associated with the resource based upon that of the installed hardware device. A resource identifier for the resource, however, is preserved so that any computer application that relies on the resource can still access the resource without additional manual reconfiguration of the resource or the computer application. Consequently, maintenance operations are substantially simplified and expedited, thereby facilitating system maintenance and minimizing computer downtime.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method dispatch multiple copies of a producer instruction to multiple execution units in a processor whenever it is determined that the producer instruction has or is likely to have multiple consumer instructions that are dependent on the producer instruction. Thus, when the multiple consumer instructions are subsequently dispatched to the multiple execution units, the results of the producer instruction are available within those execution units, and without the necessity for any inter-execution unit or inter-microcluster result forwarding. The decision of whether to dispatch multiple copies of a producer instruction may be made at runtime, e.g., within the dispatch unit of a processor, or in the alternative, may be made during compilation of a computer program to be executed on a multi-execution unit processor.

Abstract: A circuit arrangement and method of dynamically repairing a redundant memory array utilize dynamically-determined repair information, generated from a memory test performed on the redundant memory array, along with persistently-stored repair information to repair the redundant memory array. In one implementation, for example, the persistent repair information is generated during manufacture to repair manufacturing defects in the array, with the dynamic repair information generated during a power-on reset of the array to address any additional faults arising after initial manufacture and repair of the array. Furthermore, repair of dynamically-determined errors may utilize otherwise unused redundant memory cells in a redundant memory array, thus minimizing the additional circuitry required to implement dynamic repair functionality with an array.

Abstract: A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatible with the multi-way set associative cache. Class prediction may be performed using a class predict data structure with a plurality of predict array elements partitioned into sub-arrays that is accessed using a hashing algorithm to retrieve selected sub-arrays. In addition, a master/slave class predict architecture may be utilized to permit concurrent access to class predict information by multiple memory access request sources. Moreover, a cache may be configured to operate in multiple associativity modes by selectively utilizing either class predict information or address information related to a memory access request in the generation of an index into the cache data array.

Abstract: A computer system and method manipulate multiple windows or similar graphical user interface components using a proximity pointer that concurrently manipulates windows that are at least partially disposed within a proximity range located proximate the pointer. Windows may be concurrently moved or resized in response to movement of the pointer. In the alternative, windows may be concurrently moved or resized either inwardly or outwardly along radial lines extending from a common origin located proximate the pointer.

Abstract: A networked computer system and method of communicating classify request packets into multiple classes, with one class devoted to non-propagable requests that may be handled locally by destination nodes in the computer system. The multiple classes of requests are separately handled in the networked computer system such that an inability of a node to handle a request in another class does not hinder the ability of the node to process non-propagable requests, thereby avoiding deadlocks in the computer system.

Abstract: A sorting algorithm is applied to an array data structure to arrange array elements according to the predicted frequency by which those array elements are likely to be modified. Higher modification frequency array elements are arranged proximate the end of the array to minimize the number of array elements that will typically need to be updated in response to modification of these array elements, reserving the modifications that require more array elements to be updated to those array elements that have a lower likelihood of modification. A sorting algorithm suitable for use in memory compression arranges blocks for a given page in reverse order since data located proximate the beginning of a page has a higher probability of being modified than the data proximate the end of the page.

Abstract: A circuit arrangement and method vary in response to temperature changes the signal swing of an input signal to an analog circuit which has a temperature-dependent effective linear signal range. A variable gain circuit varies the signal swing of the input signal in response to a control signal supplied thereto by a temperature control circuit so that the signal swing tracks changes in the effective linear signal range of the analog circuit. In this manner, signal to noise ratio may be optimized and distortion may be minimized over a range of operating temperatures for the analog circuit.

Abstract: The invention provides a locking bail that when in the locked position prevents the removal of an optical link module from a host system and when in the unlocked position provides a handle that facilitates the removal of an optical link module. By providing a locking bail, the packing density of modules in a host may be increased. The bail provides a handle which is accessible from the front of the module when the module is unlocked. The locking bail typically engages inclined planes on latch arms that secure an optical link module to the host system.

Abstract: A compiler and method of compiling provide extended redundant copy elimination by eliminating copy statements having provably equivalent data items when it is determined that the defined operand of a copy statement has both a non-uniquely reachable use, and an additional, uniquely reachable use that is also a copy statement.

Abstract: A plurality of high speed differential output drivers are coupled to a reference current generator such that each output driver receives a substantially identical copy of a reference current signal for controlling one or more operational parameters (e.g., the propagation delay or skew) of the output driver. Multiple copies of the reference current signal are generated within the same region of an integrated circuit chip, thereby minimizing any process variations within the chip that might cause variances between the individual copies of the reference current signal. Each differential output driver has a differential pair of transistors that are coupled to ground or supply voltage through a common mode resistor that controls the common mode component of the driver output independent of the voltage swing of the output.