Abstract: The location of a land-based radio frequency (RF) emitter is determined from an airborne platform. RF signaling is received from the RF emitter via first and second antennas. In response to the received RF signaling, signal samples for both antennas are produced and processed to determine the location of the RF emitter.

Abstract: Large data sets are analyzed by hierarchical clustering using correlation as a similarity measure. This provides results that are superior to those obtained using a Euclidean distance similarity measure. A spatial continuity constraint may be applied in hierarchical clustering analysis of images.

Abstract: A yaw angle error of a motion measurement system carried on an aircraft for navigation is estimated from Doppler radar images captured using the aircraft. At least two radar pulses aimed at respectively different physical locations in a targeted area are transmitted from a radar antenna carried on the aircraft. At least two Doppler radar images that respectively correspond to the at least two transmitted radar pulses are produced. These images are used to produce an estimate of the yaw angle error.

Abstract: Piecewise conversion of an analog input signal is performed utilizing a plurality of relatively lower bit resolution A/D conversions. The results of this piecewise conversion are interpreted to achieve a relatively higher bit resolution A/D conversion without sampling frequency penalty.

Abstract: In message passing implementations, associative matching structures are used to permit list entries to be searched in parallel fashion, thereby avoiding the delay of linear list traversal. List management capabilities are provided to support list entry turnover semantics and priority ordering semantics.

Abstract: Motion measurement errors that extend beyond the range resolution of a synthetic aperture radar (SAR) can be corrected by effectively decreasing the range resolution of the SAR in order to permit measurement of the error. Range profiles can be compared across the slow-time dimension of the input data in order to estimate the error. Once the error has been determined, appropriate frequency and phase correction can be applied to the uncompressed input data, after which range and azimuth compression can be performed to produce a desired SAR image.

Abstract: The time delay and/or phase of a communication signal received by a digital communication receiver can be estimated based on a convolutional decoding operation that the communication receiver performs on the received communication signal. If the original transmitted communication signal has been spread according to a spreading operation, a corresponding despreading operation can be integrated into the convolutional decoding operation.

Abstract: A wavefront curvature effect associated with a complex image produced by a synthetic aperture radar (SAR) can be mitigated based on which of a plurality of possible flight paths is taken by the SAR when capturing the image. The mitigation can be performed differently for different ones of the flight paths.

Abstract: High resolution SAR images of a target scene at near video rates can be produced by using overlapped, but nevertheless, full-size synthetic apertures. The SAR images, which respectively correspond to the apertures, can be analyzed in sequence to permit detection of movement in the target scene.

Abstract: A desired rotation of a synthetic aperture radar (SAR) image can be facilitated by adjusting a SAR data collection operation based on the desired rotation. The SAR data collected by the adjusted SAR data collection operation can be efficiently exploited to form therefrom a SAR image having the desired rotational orientation.

Abstract: Two-dimensional SAR data can be processed into a rectangular grid format by subjecting the SAR data to a Fourier transform operation, and thereafter to a corresponding interpolation operation. Because the interpolation operation follows the Fourier transform operation, the interpolation operation can be simplified, and the effect of interpolation errors can be diminished. This provides for the possibility of both reducing the re-grid processing time, and improving the image quality.

Abstract: Motion measurement errors that extend beyond the range resolution of a synthetic aperture radar (SAR) can be corrected by effectively decreasing the range resolution of the SAR in order to permit measurement of the error. Range profiles can be compared across the slow-time dimension of the input data in order to estimate the error. Once the error has been determined, appropriate frequency and phase correction can be applied to the uncompressed input data, after which range and azimuth compression can be performed to produce a desired SAR image.

Abstract: A data processing device comprising comprising a memory having a plurality of addressable memory locations, a processor circuit, an input register operative to hold input data, an output register operative to hold output data, and a direct memory access (DMA) circuit operative to receive input data from the input register for storing the input data in a first memory location and to concurrently send output data from a second memory location to said output register. Other devices, systems and methods are also disclosed.

Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an arithmetic logic unit connected to the memory, operative to perform an arithmetic operation on data received by the arithmetic unit. An instruction decode and control unit connected to the memory, having an instruction register operative to hold a program instruction, is operative to decode a program instruction providing control signals to control the operations of the data processing device and to initiate a interrupt sequence responsive to an instruction code having a interrupt instruction. A program sequencer circuit connected to the memory, having a program register operative to hold a program counter corresponding to a program address is operative to access the memory with the program register to obtain the program instruction corresponding to the program address.

Abstract: An electronic device having addressable storage elements and a bus so that the storage elements are accessible via the bus, an address register connected to the bus, a data register connected to the bus, terminals for serial scan-in and scan-out, a scanable emulation control register coupled to the terminals, and a selecting circuit responsive to bits in the emulation control register for coupling the address register and the data register to the terminals to enable scanning of the address and data registers.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: An output boundary scan cell includes an output buffer structure (51) connected between a shared capture/shift memory (17) and an output terminal. The output buffer structure is responsive to initiation of a test mode of operation for latching at the output terminal functional test data from the shared capture/shift memory, and is operable to resolve voltage contention at the output terminal.

Abstract: In a pipelined data processor (11), an address pipeline (39, 41) is provided to hold the addresses of the instructions presently in the instruction pipeline (23, 25). The address pipeline facilitates tracing only executed instructions, and permits stopping the data processor during a branch delay slot without losing the branch information.

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external terminal thereof, which signal path includes a memory element (121, 123, 127). The memory element includes the buffer (11, 19, 21) that drives signals to/from the terminal.

Abstract: An output boundary scan cell includes an output buffer structure (51) connected between a shared capture/shift memory (17) and an output terminal. The output buffer structure is responsive to initiation of a test mode of operation for latching at the output terminal functional test data from the shared capture/shift memory and for isolating the output terminal from test data subsequently stored in the shared capture/shift memory during the test mode of operation.