Abstract: The present invention relates to a method of planarizing a film of a semiconductor device, which can improve the yield of the device by improving the planarizing in a way that coats a photoresist on an insulating film having a high topology, entirely exposes it using low energy, maintains the photoresist at the valley portion of the insulating film during the development process and then etches the opened insulating film using the remaining photoresist as an etching barrier.
Abstract: The memory cell array of the present invention has a plurality of memory cell, four memory cells hold a junction region in common. In the each memory cell, a portion of the tunnel oxide layer overlapped with the junction region is thinner than the other portion so that an individual programming operation of the each memory cell can be performed and an integration density of device can be increased.