Abstract: A pattern-based policy method for service component architecture (SCA) defines a policy pattern for SCA. The policy pattern includes a plurality of roles and one or more constraints between said plurality of roles. Each of said plurality of roles defines a plurality of intents or policy sets or combination thereof. One or more roles assigned to said one or more SCA components are identified and one or more intents or policy sets or combination thereof associated with said one or more roles are automatically applied to said one or more SCA components. Said one or more intents or policy sets or combination thereof applied to said one or more SCA components are validated based on said one or more constraints.

Abstract: A method is disclosed that employs a hierarchical path database generator for accessing internal signal or port names in a design hierarchy of an integrated circuit design. The method comprises the steps of inputting design files into the hierarchical path database generator; and said hierarchical path database generator determining ports and signals in said design files, and storing the names of said ports and signals in a hierarchical database in a logical hierarchical order. The method comprises the further steps of providing a testcase to verify a defined aspect of the integrated circuit design; parsing the testcase to identify all signal and port names therein; and for each of the signal and port names identified in the testcase, inputting said each name into the hierarchical path database generator, and obtaining from that generator a hierarchical path associated with said each signal and port name.

Abstract: The invention relates to adenozin A3 receptor ligands labeled with iodine isotops of mass number 125, within those favorably to antagonists and their isomers, to the experimental materials containing them, to a process for the preparation of the compounds of the general formula (I) and their isomers, to the new intermediates of the general formula (II) and to the preparation thereof.

Abstract: A finFET and its method for fabrication include a gate electrode formed over a channel region of a semiconductor fin. The semiconductor fin has a crystallographic orientation and an axially specific piezoresistance coefficient. The gate electrode is formed with an intrinsic stress determined to influence, and preferably optimize, charge carrier mobility within the channel region. To that end, the intrinsic stress preferably provides induced axial stresses within the gate electrode and semiconductor fin channel region that complement the axially specific piezoresistance coefficient.

Abstract: A semiconductor structure in which the contact resistance in the contact opening is reduced as well as a method of forming the same are provided. This is achieved in the present invention by replacing conventional contact metallurgy, such as tungsten, or a metal silicide, such as Ni silicide or Cu silicide, with a metal germanide-containing contact material. The term “metal germanide-containing” is used in the present application to denote a pure metal germanide (i.e., MGe alloy) or a metal germanide that includes Si (i.e., MSiGe alloy).

Abstract: In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.

Abstract: A method of in system diagnostics through scan matrix, and an integrated circuit chip in which the diagnostics are performed, are disclosed. The integrated circuit chip operable in a plurality of Boundary Scan test modes in which at least a part of the circuitry in the integrated circuit chip is tested, the integrated circuit chip comprises a scan matrix controller and an instruction register. The scan matrix controller is provided for partitioning said circuitry into multiple matrices, each of the matrices having a plurality of scan elements. The instruction register is provided for holding instructions for the scan matrix controller for partitioning the chip into said multiple matrices. The scan matrix controller is further arranged to test each of said matrices according to instructions in the instruction register by applying a test signal to the tested part of the circuitry.

Abstract: An automatic, self-contained device for detecting toxic agents in a water supply includes an analyzer for detecting at least one toxic agent in a water sample, introducing means for introducing a water sample into the analyzer and discharging the water sample from the analyzer, holding means for holding a water sample for a pre-selected period of time before the water sample is introduced into the analyzer, and an electronics package that analyzes raw data from the analyzer and emits a signal indicating the presence of at least one toxic agent in the water sample.

Abstract: An optical scanner for use in conjunction with an infrared spectrometer is disclosed. The optical scanner translates a beam of radiation to a stationary spot on a traveling sheet of material so that ample integration time within the spectrometer is achieved. The beam path impinges on the traveling web and the radiation is reflected off the traveling web back through the optical scanner and recombined at an interferometer. The beam of radiation is kept stationary with respect to both the traveling sheet and the carriage which houses the spectrometer.

Abstract: The present invention provides a semiconductor structure that includes a high performance field effect transistor (FET) on a semiconductor-on-insulator (SOI) in which the insulator thereof is a stress-inducing material of a preselected geometry. Such a structure achieves performance enhancement from uniaxial stress, and the stress in the channel is not dependent on the layout design of the local contacts. In broad terms, the present invention relates to a semiconductor structure that comprises an upper semiconductor layer and a bottom semiconductor layer, wherein said upper semiconductor layer is separated from said bottom semiconductor layer in at least one region by a stress-inducing insulator having a preselected geometric shape, said stress-inducing insulator exerting a strain on the upper semiconductor layer.

Abstract: A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

Abstract: Target subtree setting means sets a target subtree relating to a content portion. Occurrence mode detecting means collates a target subtree relating to a content with a tree relating to each of past structured/hierarchical contents and detects an occurrence mode of each node of the target subtree. Statistical information generating means generates statistical information concerning an occurrence frequency of the occurrence mode of each node in the target subtree. Classifying means classifies each node of the target subtree based on the statistical information and a result of detecting the occurrence mode. Matching pattern generating means generates the matching pattern for the target content portion based on the classification. The structured/hierarchical contents are identified by use of the matching pattern.

Abstract: A method for fabricating a hybrid orientation substrate provides for: (1) a horizontal epitaxial augmentation of a masked surface semiconductor layer that leaves exposed a portion of a base semiconductor substrate; and (2) a vertical epitaxial augmentation of the exposed portion of the base semiconductor substrate. The resulting surface semiconductor layer and epitaxial surface semiconductor layer adjoin with an interface that is not perpendicular to the base semiconductor substrate. The method also includes implanting through the surface semiconductor layer and the epitaxial surface semiconductor layer a dielectric forming ion to provide a buried dielectric layer that separates the surface semiconductor layer and the epitaxial surface semiconductor layer from the base semiconductor substrate.

Abstract: A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer.

Abstract: An electrical fuse programming circuit and a method for programming an electrical fuse within the electrical fuse programming circuit use a programming circuit bus to which are electrically connected in parallel the electrical fuse and a bypass resistor. A current within the programming circuit bus is made to flow through the bypass resistor for a period of time sufficient to stabilize the current, and then sequentially and instantaneously switched to program the electrical fuse.

Abstract: A technique for determining whether a server host supports the functions in a command sent by a client host. The client host formulates a command including a command object that contains parameter objects. The parameter objects, which represent the functions, are serialized, e.g., using the Java serialization command, and communicated to the server host. The server host attempts to deserialize the parameter objects. If it is successful, it is concluded that the server host supports the functions represented by the parameter objects. Or, it is concluded that the server host is incompatible with the functions represented by one or more parameter objects that cannot be deserialized. The server host may be a storage server, and the functions may be storage-related, such as a copy type to be performed.

Abstract: An integrated circuit design, structure and method for fabrication Thereof includes at least one logic device layer and at least two additional separate memory array layers. Each of the logic device layer and the at least two memory array layers is independently optimized for a particular type of logic device or memory device disposed therein. Preferably also disposed within the logic device layer are array sense amplifiers, memory array output drivers and like higher performance circuitry otherwise generally disposed within memory array layer substrates. All layers may be independently powered to provide additional performance enhancement.

Abstract: A telephone device such as a speaker phone or message recording device is remotely controlled either as a standalone device or as part of a security system. The telephone device can be controlled by a key fob or other user-operated transmitter that a user actuates to answer a call by speaker phone, end a call, place a call, or control functions of the message recording device such as playing back messages. The key fob transmits a wireless signal that is received and processed by a security system. In response, the security system controls the telephone device. The key fob may control security functions as well. In another approach, the key fob may control the telephone device directly without intervention of a security system. Or, the key fob may control the telephone device via a home automation network.

Abstract: A SOI MOSFET structure having a reduced step height between the various semiconductor layers without adversely affecting the junction capacitance of the semiconductor device formed on the uppermost semiconductor layer as well as a method of fabricating the same are provided. The structure of the present invention includes an elevated device region having at least one semiconductor device located on a second semiconductor layer. The elevated device region further includes a source/drain junction that extends from the second semiconductor layer down to a first buried insulator layer that is located on an upper surface of the semiconductor substrate. The structure also includes a recessed device region having at least one semiconductor device located atop a first semiconductor layer which is located on an upper surface of the first buried insulator. An isolation region separates the elevated device region from the recessed device region.

Abstract: An electronic watch 400 which comprises a power supply 401 and a watch circuit 402.