Abstract: A method (and structure) senses a rotational vibration of a disk drive. The disk drive includes a rotating disk. The disk includes a plurality of reference bits across a surface thereof. The method (and structure) includes detecting the reference bits across a pattern on the rotating disk, and analyzing a time interval between adjacent ones of the reference bits.

Abstract: A disk drive system (and method) includes an actuator system including a first voice coil motor (VCM), a second voice coil motor for enhancing dynamic resonance properties of the actuator system, and a single error position detecting mechanism, thereby enabling a higher bandwidth servo system configured with a single position error detection source.

Abstract: A segment announcing system is disclosed that contains one or more segment announcement receivers that receive one or more announcements over a network connection and/or other communication connection. The announcements contain content information about the content of broadcast information being broadcast, e.g., to a television. The segment announcement receivers have one or more control outputs to perform a function, typically to control the segment announcement receivers during processing of information called a content stream.

Abstract: A cache bypass mechanism automatically avoids caching of data for instructions whose data references, for whatever reason, exhibit low cache hit ratio. The mechanism keeps a record of an instruction's behavior in the immediate past, and this record is used to decide whether its future references should be cached or not. If an instruction is experiencing bad cache hit ratio, it is marked as non-cacheable, and its data references are made to bypass the cache. This avoids the additional penalty of unnecessarily fetching the remaining words in the line, reduces the demand on the memory bandwidth, avoids flushing the cache of useful data and, in parallel processing environments, prevents line thrashing. The cache management scheme is automatic and requires no compiler or user intervention.

Abstract: Buffers are provided in two elements between which data is to be transferred wherein both buffers are managed solely by the originator of the data transfer. Only one transfer is required to transmit a message, and a second transfer acknowledges the completion of the function because message delivery to the receiver is guaranteed under the implemented protocol. When a request is sent, a message timer is started at the sender. When the normal response for the request is received, the timer is reset; however, if the duration of the message operation exceeds the timeout value, a message-timeout procedure is initiated. When the cancel command is issued, a second timer is set. If this timer is exceeded, subsequent cancel commands can be issued. If subsequent cancel commands are issued, a cancel complete command must be sent and responded to.

Abstract: A technique and a mechanism accurately determines the correct prefetch line for loops with strides of 1, N, or a combination of stride values. Stride registers are used to assist in prefetching. Furthermore, stride register values can be used to specify "cacheability" of data on an object by object basis to prevent "cache flushing". The compiler uses a new instruction, "MOVE GPR TO STRIDE REGISTER", prior to a loop to insert the "calculated stride value(s)" into the stride register(s) associated with the index register(s) which will be incremented by that stride value. At the end of the loop, a second new instruction, "CLEAR STRIDE REGISTER SET", is used to place a value of zero in all of the stride registers to inhibit prefetching of data which would most likely not be used. A zero value in the stride registers inhibits prefetching. Non-zero values in the stride registers clearly mark the execution of a loop, which is where prefetching makes the most sense.