Patents Represented by Attorney Sean T. Calfee, Halter & Griswold Moorhead
  • Patent number: 5548763
    Abstract: A computer system having four states of power management: a normal operating state, a standby state, a suspend state, and an off state. The standby state is characterized by devices, such as a video controller and a hard drive, being placed into a low-power mode transparent to the operating system and the applications executing on the computer system. The suspend state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive. Later, after system power is restored, the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected. The normal operating state and the off state correspond to the typical on and off states of more conventional computer systems.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: August 20, 1996
    Assignee: International Business Machines Corporation
    Inventors: James L. Combs, Dwayne T. Crump, Steven T. Pancoast
  • Patent number: 5544334
    Abstract: A computer system having: a central processing unit (CPU), having a system bus associated therewith, a first bus interface circuit (BIC) in circuit communication with the CPU and generating a peripheral bus, such as the MICRO CHANNEL bus, a floppy drive controller (FDC), and an Integrated Drive Electronics (IDE) hardfile (hard drive). The IDE hardfile is in electrical circuit communication with the peripheral bus via a second bus interface circuit. The second bus interface circuit includes a writable latch having at least two states and in circuit communication with the peripheral bus. The latch states are selectable by the CPU via the system bus. The second bus interface circuit also has an access control circuit in circuit communication with the peripheral bus, the system bus, and the latch for selectively allowing data transfers between the CPU and either the FDC or the IDE hard drive, depending on the state of the latch.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: August 6, 1996
    Assignee: International Business Machines Corporation
    Inventor: Mark G. Noll