Abstract: A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.

Abstract: A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.

Abstract: A method is disclosed to improve the reliability of copper damascene interconnects. This is accomplished by performing a two-stage anneal of the copper metal; first, after the deposition of copper in the damascene, and then for the second time, after the removal of excess copper by chemical mechanical polishing.

Abstract: A method is provided to reduce poly depletion in MOS transistors. Conventionally, after a polysilicon electrode has been doped, an anneal step is usually performed to activate the dopants. However, the anneal step may be insufficient to drive the implanted impurities down the entire depth of the polysilicon electrode. Consequently, a portion of the polysilicon gate nearest to the gate oxide will be depleted of dopants. This poly depletion will have a detrimental effect on the control of the threshold voltage, and hence on the performance of the device. It is disclosed in the present invention a method of forming polysilicon gates where dopant depletion at the interface near the gate oxide layer is alleviated substantially by using laser annealing; however, by first pre-amorphizing the polycrystalline silicon prior to ion (implantation to a desired depth such that during laser annealing the dopants will diffuse uniformly to a melt depth.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased coupling ratio and improved program speed. A split-gate cell is also provided where the a first polysilicon layer forms the floating gate disposed over an intervening intergate oxide formed over a second polysilicon layer forming the control gate. However, the second polysilicon layer is also formed over the source region and overlying the other otherwise exposed portion of the floating gate such that this additional poly line now shares the voltage between the source and the floating gate, thereby reducing punch-through and junction breakdown voltages. In addition, the presence of another poly wall along the floating gate increases the coupling ratio between the source and the floating gate, which in turn improves program speed of the split-gate flash memory cell.

Abstract: A method is provided for forming a split-gate flash memory cell having reduced size, increased capacitive coupling and improved data retention capability. A split gate cell is also provided with appropriate gate oxide thicknesses between the substrate and the floating gate and between the float gate and the control gate along with an extra thin nitride layer formed judiciously over the primary gate oxide layer in order to overcome the problems of low data retention capacity of the floating gate and the reduced capacitive coupling between the floating gate and the source of prior art.

Abstract: A method is disclosed for forming self-aligned, borderless contact and vias together and simultaneously with relaxed photolithographic alignment tolerances using a modified dual damascene process having two etch-stop layers. A first etch-stop layer is formed over a first dielectric layer. A second dielectric layer and a second etch-stop layer are next formed sequentially over the first etch-stop layer. Contact/via hole pattern is etched into the first etch-stop layer using a first photoresist layer. A second photoresist layer, patterned with metal line trench pattern, is formed over the contact/via patterned first etch-stop layer. The contact/via hole openings are etched into the first dielectric layer until the second etch-stop layer is reached. Then, both the first and second etch-stop layers are etched through the openings.

Abstract: A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Abstract: A method for fabricating contact holes in high density integrated circuits and the resulting structure are disclosed. It is shown that by judiciously integrating the process of forming shallow tapered holes with self-alignment techniques, self-aligned holes can be fabricated with reduced number of masking process steps. This is accomplished by first forming shallow tapered holes to a certain depth over certain regions in a substrate by means of isotropic etching and then extending them by anisotropic etching to full depth corresponding to the regions they are allowed to contact. The net result is a whole set of holes which are self-aligned and which are formed by means of a single photoresist mask.