Abstract: A method to reduce via poisoning in low-k copper dual damascene interconnects through ultraviolet (UV) irradiation of the damascene structure is disclosed. This is accomplished by irradiating the insulative layers each time the layers are etched to form a portion of the damascene structure. Thus, irradiation is performed once after the forming of a trench or a via, and again for the second time when the insulative layers are etched to form the remaining trench or via. The trench and hole openings of the dual damascene structure are exposed to UV light in a dry ozone environment, which then favorably alters the surface characteristics of the low-k dielectric walls which are normally hydrophobic. Hence, during etching, moisture is not absorbed into the walls.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a protruding source in place of the conventional flat source. The vertically protruding source structure has a top portion and a bottom portion. The bottom portion is polysilicon while the top portion is poly-oxide. The vertical wall of the protruding structure over the source is used to form vertical floating gate and spacer control gate with an intervening inter-gate oxide. Because the coupling between the source and the floating gate is now provided through the vertical wall, the coupling area is much larger than with conventional flat source. Furthermore, there is no longer the problem of voltage punch-through between the source and the drain. The vertical floating gate is also made thin so that the resulting thin and sharp poly-tip enhances further the erasing and programming speed of the flash memory cell.

Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

Abstract: A method of fabricating a CVD Ta2O5/Oxynitride stacked gate insulator with TiN gate electrode for subquarter micron MOSFETs is disclosed. In a first embodiment, the surface of a silicon substrate is reacted in N2O or NC ambient to form an oxynitride layer. Tantalum oxide is next chemical vapor deposited, thus forming a Ta2O5/Oxynitride stacked gate insulator. The stacked gate is then completed by depositing titanium nitride as the gate electrode and then patterning and forming the gate structure. In the second embodiment, a gate oxide is first formed on the silicon substrate. Then the gate oxide layer is nitridated in N2O or NO ambient to form the oxynitridated layer, thus forming a two-step oxynitride layer. The tantalum oxide layer and the titanium nitride gate electrode are formed as in the first embodiment.

Abstract: A method for improving the electrical resistance of contacting surfaces in via holes in semiconductor substrates is disclosed. The via holes are formed and later filled with metal to interconnect metal layers in the substrate. The method involves the deposition of interconnect metal at two different stages of two different temperatures. In another embodiment, after sputter etch cleaning, one layer of specific thickness of interconnect metal is deposited at a specific temperature range.

Abstract: A method is disclosed for forming a split-gate flash memory cell having a salicidated control gate and self-aligned contacts. Salicidation is normally performed with single gate devices, such as logic devices. In a split-gate where the control gate overlays the floating gate with an intervening intergate oxide layer, it is conventionally incompatible to form self-aligned silicides over the control gate due to its position at a different level from that of the floating gate. Furthermore, oxide spacers that are normally used are inadequate when applied to memory cells. It is shown in the present invention that by a judicious use of an additional nitride/oxide layer over the control gate, oxide spacers can now be used effectively to delineate areas on the control gate that can be silicided and also self-aligned.

Abstract: A plasma damage protection cell using floating N/P/N and P/N/P structure, and a method to form the same are disclosed. Floating structures of the protection cell and the floating gates for the MOS devices are formed simultaneously on a semiconductor substrate having shallow trench isolation. The floating structures are implanted separately to form the N/P/N and P/N/P bipolar base, emitter and collector regions while the source/drain of the respective NMOS and PMOS devices are implanted with appropriate sequencing. The floating structures are connected to the substrate with appropriate polarity to provide protection at low leakage current levels and with tunable punch-through voltages.

Abstract: A PIP (Poly-Interpoly-Poly) capacitor with high capacitance is provided in a split-gate flash memory cell. A method is also disclosed to form the same PIP capacitor where the bottom and top plates of the capacitor are formed simultaneously with the floating gate and control gate, respectively, of the split-gate flash memory cell. Furthermore, the thin interpoly oxide of the cell, rather than the thick poly-oxide over the floating gate is used as the insulator between the plates of the capacitor. The resulting capacitor yields high storage capacity through high capacitance per unit area.

Abstract: A flash memory cell and the making thereof is disclosed where the cell has a damascene-like stacked gate. The stacked gate is formed not by blanket depositing a first polysilicon layer and then subtractively etching to form a floating gate followed by the depositing of a second polysilicon layer separated by an intervening inter-gate dielectric layer over the floating gate. On the contrary, a trench is formed in a nitride layer formed over a substrate using a modified damascene process. The first polysilicon layer is conformally deposited into the damascene-like trench to form the floating gate of the disclosed cell. Then, a layer of inter-gate dielectric layer is formed over the first polysilicon layer in the trench, followed by the forming of a second polysilicon layer over the dielectric layer, thus forming the damascene-like stacked gate of this invention.

Abstract: A novel method of forming a polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notched nitride layer over the tip. At the same time, a method of forming a self-aligned source (SAS) line is disclosed. A relatively thin polygate is formed so as to decrease the growth of the protrusion of conventional gate bird's beak (GBB) to a smaller and sharper tip. It will be known by those skilled in the art that GBB is easily damaged during conventional poly etching where polyoxide is used as a hard mask. To use polyoxide as a hard mask, thick polysilicon is needed in the first place. Such thick poly will increase gate coupling ratio, which has the attendant effect of degrading program and erasing performance of the memory cell.

Abstract: A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by depositing a poly-2 layer to form a spacer floating gate adjacent to the control gate with an intervening intergate oxide layer. The source is self-aligned and the floating gate is also formed to be self-aligned to the control gate, thus making it possible to reduce the cell size. The resulting self-aligned source alleviates punch-through from source to control gate while the self-aligned floating gate with respect to the control gate provides improved programmability. The method also replaces the conventional poly oxidation process thereby yielding improved sharp peak of floating gate for improved erasing and writing of the split-gate flash memory cell.

Abstract: A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched to form a step adjacent to the side-wall of a floating gate underlying the polyoxide. A spacer is next formed of a hot temperature oxide over the step poly. An interpoly oxynitride is then formed and control gate is patterned overlapping the floating gate with the intervening interpoly oxide. The step poly and the spacer thereon form proper distances between the control gate and the floating gate while keeping the distance between the poly tip and the control gate unchanged so that appropriate couplings between the control gate and the floating gate, and between the floating gate and the substrate are achieved, thus improving the over-all performance of the split-gate flash memory having a step poly.

Abstract: A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area.

Abstract: A method is provided for forming a source line self-aligned to adjacent transistor device. This is accomplished by a forming a self-aligned polysilicon as a source line in an opening formed in a doped polysilicon layer separated from the source line by a spacer. The alignment of the poly source line with the transistor is provided by employing still another thin polysilicon layer as a mask for etching the source opening in the doped polysilicon layer which already has an outside wall aligned with respect to the contact hole for the drain of the device. An additional spacer is provided between the outside wall of the doped poly and the drain contact.

Abstract: A method and structure are disclosed related to tapered contact holes in VLSI and ULSI technologies. The contact hole is formed by taking advantage of two-tiered polycide lines formed with a step. The polycide lines with steps are further formed with oxide spacers. The resulting structure is then used to form contact hole in between the oxide spacers. Because the oxide spacers are used—without the need for a tightly toleranced mask—to delimit the area of the contact at the bottom of the hole, a larger area of contact is obtained in addition to the tapered edges that are formed. Polycide is chosen to be a multilayer structure comprising tungsten-silicide (WSi2) over poly-silicon (poly-Si). Next, polycide is patterned by etching with a recipe which etches the WSi2 faster than it etches the underlying poly-Si. The etching, therefore, results in a structure where the WSi2 forms a step over the poly-Si layer.

Abstract: A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to word line. This multi-self-aligned structure, which provides the maximum shrinkage of the cell that is possible, is also disclosed. The multi-self-alignment is accomplished by first defining the floating gate at the same time the trench isolation is formed, and then self-aligning the source to the floating gate by using a nitride layer as a hard mask in place of the traditional polyoxide, and finally forming a polysilicon spacer to align the word line to the floating gate. Furthermore, a thin floating gate is used to form a thin and sharp poly tip through the use of a “smiling effect” to advantage.