Abstract: A content addressable memory (CAM) device having a range compare function. A boundary value is stored within a plurality of CAM cells within the CAM device. A range compare operation is performed to determine whether a comparand is greater than the boundary value. A result signal is asserted if the comparand is greater than the boundary value.

Abstract: An intermediate server or system having knowledge of application program protocols used by the application programs in a person's (i.e., user's) wireless device is used to translate information communicated with the device in accordance with a transport-level protocol and the same information communicated with a remote server or system that services the application program in use by that person.

Abstract: A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the CAM cells, and the column parity storage elements store column parity values that correspond to respective columns of the CAM cells. A bit error in the array is detected through row and column parity checking that uniquely identifies the row and column location of the error and enables correction of the error.

Abstract: An apparatus and method are described for real-time buying and selling of bandwidth at differentiated quality of service levels, routing of excess traffic over the bandwidth purchased in real time, and billing and settlement of the transactions. In the present invention, a network user buys bandwidth to have a fixed capacity level. When the current traffic level exceeds the fixed capacity level, the network user buys additional capacity in real time as needed to handle the overflow. In addition, when the fixed capacity level exceeds the current traffic level, the network user can sell the excess capacity as available. Further, network users can select among a number of response times. The response times, which can be guaranteed, allow all traffic to be delivered within a time limit, or set time limits within which different types of data can be delivered.

Abstract: A method and apparatus are described for the filtering of a common input string to generate various filtered comparand strings. The filtering of a common input string enables concurrent lookups in different tables to be performed on multiple filtered comparands by different CAM devices (or different blocks within a CAM device), to compare the data in the filtered comparand strings with data stored in its associative memory. By performing multiple lookups in parallel, rather than sequentially, packet throughput in a CAM may be significantly increased.

Abstract: A CAM device to perform in one clock cycle: (1) receive comparand data from a comparand bus; (2) receive an instruction; (3) perform the comparison of the comparand data with a first group of CAM cells; (4) generate a match address for a location in the CAM array that stores data matching the comparand data; (5) access data stored in a second group of the CAM cells in the CAM array, wherein the second group of CAM cells may store data associated with the matched location; and (6) output to an output bus the match address, the data stored in the second group of CAM cells, and/or status information corresponding to the matched address or the second group of CAM cells.

Abstract: A memory system includes physical memory devices or ranks of memory devices that can be set to reduced power modes. In one embodiment, a hardware memory controller receives memory instructions in terms of a logical address space. In response to the relative usages of different addresses within the logical address space, the memory controller maps the logical address space to physical memory in a way that reduces the number of memory devices that are being used. Other memory devices are then set to reduced power modes. In another embodiment, an operating system maintains a free page list indicating portions of physical memory that are not currently allocated. The operating system periodically sorts this list by group, where each group corresponds to a set or rank of memory devices. The groups are sorted in order from those receiving the heaviest usage to those receiving the lightest usage.

Abstract: A method and apparatus for generating an agent schedule for a multi-contact center that has immediate queues and deferred queues. In one embodiment, a method includes scheduling software receiving a plurality of scheduling data from a user interface, and the scheduling software generating a plurality of scheduling constraints. The method further includes a search engine using the plurality of scheduling constraints to generate a plurality of potential schedules including first potential schedules for immediate queues, and second potential schedules for deferred queues. The method further includes performing a first analysis on the first potential schedules to generate first estimated service levels, and performing a second analysis on the second potential schedules to generate second estimated service levels, wherein the first estimated service levels and the second estimated service levels are expressed in interchangeable units.

Abstract: A semiconductor package with solder bumps and a method for making the same are described. One embodiment comprises a flip-chip design with a rectangular semiconductor die with a relatively large aspect ratio bonded to a substantially square substrate through solder bumps. In one embodiment, active bumps are concentrated in an area relatively close to the neutral point of the die, for example, in a substantially square area about the neutral point.

Abstract: A computing device is provided that includes a display comprising a plurality of discrete elements. A memory is used to store a data collection of paginated content. A processor of the computing device is configured to retrieve each of the pages from the memory. The processor signals the display to individually present each of the pages. A sensor device is coupled to the processor. The sensor device is deflectable to signal the processor a deflection value that causes the processor to sequentially present at least portions of multiple pages on the display.

Abstract: A content addressable memory (CAM) device comprising a plurality of CAM blocks and a block control circuit. The plurality of CAM blocks each includes an array of CAM cells to store data words and an array of priority number storage circuits to store priority numbers. Each priority number indicates a priority of a respective one of the data words relative to others of the data words. The block control circuit has an input to receive a class code and circuitry to output a plurality of select signals to the plurality of CAM blocks. Each select signal selectively disables a respective one of the plurality of CAM blocks from participating in a compare operation according to the class code.

Abstract: An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.

Abstract: A content addressable memory (CAM) device with mode-selectable match detect timing. The CAM device includes a plurality of rows of CAM cells coupled to respective match lines. Storage circuits are coupled to the match lines and configured to store match indications signaled thereon in response to assertion of a first timing signal. A timing control circuit is coupled to the storage circuits and configured to assert the first timing signal at either a first instant or a second instant according to the state of a mode select signal.

Abstract: A content addressable memory (CAM) device having a memory, a hash index generator to associate a search value with a unique location within a memory, and a compare circuit. The index generator generates an index based on the search value. The memory receives the index from the index generator and outputs a stored data value from a location indicated by the index. A compare circuit receives the data value from the memory and compares the data value and the search value to generate a match signal indicative of whether the data value and search value match. The match signal and index are output from the CAM device.

Abstract: A content addressable memory (CAM) device including a CAM array and a priority index table. The CAM array has a plurality of rows of CAM cells, each row including a plurality of row segments and being adapted to store a data word that spans a selectable number of the row segments. The priority index table is coupled to the plurality of rows of CAM cells and is adapted to store a plurality of priority numbers, each priority number being indicative of a priority of a corresponding data word stored in the CAM array.

Abstract: In a semiconductor device having a semiconductor die without an ESD circuit and a separate ESD circuit and an external lead, the external lead is first bonded to the separate ESD circuit. Thereafter, the separate ESD circuit is bonded to the semiconductor die. As a result, in the process of bonding the semiconductor die, any ESD disturbance is absorbed by the ESD circuit. In addition, a semiconductor device such as a DDR DRAM memory device, has a chip carrier with a first surface having a plurality of leads and a second surface opposite to it with an aperture between them. A semiconductor die with a mounting surface and a bonding pad faces the second surface with the bonding pad in the aperture. An ESD circuit is mounted on the mounting surface in the aperture. A first electrical connector connects one of a plurality of leads to the ESD circuit and a second electrical connector connects the ESD circuit to the bonding pad.

Abstract: A method for performing differencing and updating between electronic files is provided. A byte-level file differencing algorithm receives two byte streams corresponding to an original file and a new file. The new file includes updated and revised versions of the original file. The file differencing algorithm determines a longest common sub-string (LCS) between the two byte streams and divides each of the two byte streams into sub-streams. The sub-streams include the LCS along with prefix and suffix sub-streams to the LCS. The file differencing algorithm then recursively determines an LCS and divides each sub-stream until a size of the sub-streams is less than a pre-specified size. Byte-level differences are then identified between each of the corresponding sub-streams. Further, the file differencing algorithm defines a protocol for structuring a delta file by using a set of operation codes and a variable length integer format to eliminate redundant information in the delta file.

Abstract: An electronic device is formed at least partially from a deflectable material that generates an electrical signal in response to contact. The first material is integrated with a display module to provide a shaped feature on the exterior surface of the display module. The shaped feature detects contact with an external object on one or more contact points, where contact with the contact points corresponds to a defined input for a processor of the electronic device.

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is couple to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A content addressable memory (CAM) device having a cascaded CAM array. The cascaded CAM array includes a first array of CAM cells and a second array of CAM cells. A first plurality of compare signal lines is coupled to the first array CAM cells and a second plurality of compare signal lines coupled to the second array of CAM cells. A plurality of storage elements have inputs coupled to the first plurality of compare signal lines and outputs coupled to the second plurality of compare signal lines.