Abstract: Embodiments of switched-capacitor gain stage circuits and methods of their operation are provided. The circuit includes an operational amplifier, parallel sampling capacitors, an offset storage capacitor coupled to an amplifier input, and multiple switches that are configurable to place the gain stage circuit in a sampling state, a gain state, and an output state. In the sampling state, the switches are configured so that a first charge component representing an input signal is stored on the sampling capacitors, and a second charge component representing an amplifier offset voltage is stored on the offset storage capacitor. In the gain state, the switches are configured so that a third charge component representing a finite gain of the amplifier is stored on the offset storage capacitor. In the output state, the switches are configured so that the first, second, and third charge components contribute to an output signal produced at the output node.

Abstract: 3-D ICs (18, 18?, 90) with integrated passive devices (IPDs) (38) having reduced cross-talk and high packing density are provided by stacking separately prefabricated substrates (20, 30, 34) coupled by through-substrate-vias (TSVs) (40). An active device (AD) substrate (20) has contacts on its upper portion (26). An isolator substrate (30) is bonded to the AD substrate (20) so that TSVs (4030) in the isolator substrate (30) are coupled to the contacts (26) on the AD substrate (20), and desirably has an interconnect zone (44) on its upper surface. An IPD substrate (34) is bonded to the isolator substrate (30) so that TSVs (4034) therein are coupled to the interconnect zone (44) on the isolator substrate (30) and/or TSVs (4030) therein. The IPDs (38) are formed on its upper surface and coupled by TSVs (4034, 4030) in the IPD (34) and isolator (30) substrates to devices (26) in the AD substrate (20).

Abstract: A Schottky gate (27?, 27?) of a metal-semiconductor FET (20?, 20?) is formed on a semiconductor comprising substrate (21) by, etching a gate recess (36) so as to expose a slightly depressed surface (362) of the substrate (21), the etching step also producing surface undercut cavities (363) extending laterally under the etch mask (43) from the gate recess (36), then conformally coating the slightly depressed surface (362) with a first Schottky forming conductor (40?) and substantially also coating inner surfaces (366) of the surface undercut cavities (363), and forming a Schottky contact to the semiconductor comprising substrate (21), adapted when biased to control current flow in a channel (22) extending between source (23) and drain (24) of the FET (20?, 20?) under the gate recess (36).

Abstract: Embodiments include methods and apparatus for characterizing a tuner. For a given tuner, a processing system is adapted to measure scattering parameters for a plurality of characterization points that are non-uniformly distributed across a Smith chart, and to store the scattering parameters in a tuner characterization file. Interpolation and extrapolation processes are performed to determine additional scattering parameters for a plurality of additional characterization points, which are also stored in the tuner characterization file.

Abstract: Embodiments of a semiconductor structure include a first current electrode region, a second current electrode region, and a channel region. The channel region is located between the first current electrode region and the second current electrode region, and the channel region is located in a fin structure of the semiconductor structure. A carrier transport in the channel region is generally in a horizontal direction between the first current electrode region and the second current electrode region.

Abstract: Embodiments include methods and apparatus for detecting a phase angle between an incident signal and a reflected signal. The apparatus comprises a plurality of phase shifters and additional circuitry. The plurality of phase shifters is adapted to apply first phase shifts to a representation of the incident signal and to apply second phase shifts to a representation of the reflected signal. The additional circuitry, which is operatively coupled to the plurality of phase shifters, is adapted to produce a first indication of a location of a relative phase difference between the incident signal and the reflected signal within a first region of a first reference circle, and to produce a second indication of the location of the relative phase difference within a second region of a second reference circle, wherein the second reference circle is rotated with respect to the first reference circle.

Abstract: An embodiment of a calibration standard includes a substrate, a set of conductive structures fabricated on the substrate, and a conductive end structure fabricated on the substrate. The set of conductive structures include an inner conductive structure, a first outer conductive structure positioned to one side of the inner conductive structure, and a second outer conductive structure positioned to an opposite side of the inner conductive structure. The inner and outer conductive structures are aligned in parallel with each other along offset principal axes of the inner and outer conductive structures. The conductive end structure is electrically connected between an end of the first outer conductive structure and an end of the second outer conductive structure, and the conductive end structure is spatially separated from an end of the inner conductive structure at the surface of the substrate.

Abstract: Electronic elements with very low resistance back-side coupling are provided by forming one or more narrow trenches or pipes, preferably dielectric lined, in front sides of substrates, filling the trenches or pipes with a conductor having a coefficient of expansion not too different from that of the substrate but of higher conductivity, forming an epitaxial SC layer over the front side of the substrate in Ohmic contact with the conductor the trenches or pipes, forming various semiconductor (SC) devices in the epi-layer, back grinding the substrate to expose bottoms of the conductor filled trenches or pipes, and providing a back-side conductor contacting the conductor in the trenches or pipes. For silicon SCs, tungsten is a suitable conductor for filling the trenches or pipes to minimize substrate stress. Series ON-resistance of the elements due to the substrate resistance is substantially reduced.

Abstract: Electrostatic discharge (ESD) protection clamps (61, 95) for I/O terminals (22, 23) of integrated circuit (IC) cores (24) comprise a bipolar transistor (25) with an integrated Zener diode (30) coupled between the base (28) and collector (27) of the transistor (25). Prior art variations (311, 312, 313, 314) in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants (781, 782) and forming the base (28, 68) coupled anode (301, 75) and collector (27, 70, 64) coupled cathode (302, 72) of the Zener (30) using opposed edges (713, 714) of a single relatively thin mask (71, 71?). The anode (301, 75) and cathode (302, 72) are self-aligned and the width (691) of the Zener space charge region (69) therebetween is defined by the opposed edges (713, 714) substantially independent of location and orientation of the ESD clamps (61, 95) on the die or wafer.

Abstract: Embodiments include transceivers and transmit IQ imbalance correction methods. A transmitter lineup, which includes an equalizer and an RF modulator, receives a stream of baseband samples having real and imaginary components, processes the real components along a first channel, and processes the imaginary components along a second channel to produce processed real and imaginary components. The equalizer equalizes at least one of the processed real components and the processed imaginary components to compensate for offset frequency-dependent components of transmitter IQ imbalance. The RF modulator receives and modulates analog versions of the equalized samples, resulting in an analog RF signal. An embodiment also includes a balancer adapted to apply IQ gain and phase correction to the equalized samples to compensate for offset frequency-independent components of the transmitter IQ imbalance.

Abstract: A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.

Abstract: In an embodiment, a wireless communication system (100, FIG. 1) includes one or more nodes (102-108) and one or more user equipments (UE) (130-134). A node may service a cell (110-116). A UE may be classified (802, FIG. 8) into a cell-edge UE group when the UE is within in a cell-edge region (504, 506, 508, FIG. 5) of a cell. The cell-edge UE group may be allocated at least one first frequency range within an available bandwidth (600, 700, FIGS. 6 and 7). A UE may be reclassified (808, FIG. 8) into a cell-center UE group based on at least one indicator of UE performance. The cell-center UE group may be allocated at least one second frequency range within the available bandwidth.

Abstract: An improved bipolar transistor (40, 40?) is provided, manufacturable by a CMOS IC process without added steps. The improved transistor (40, 40?) comprises an emitter (48) having first (482) and second (484) portions of different depths (4821, 4841), a base (46) underlying the emitter (48) having a central portion (462) of a first base width (4623) underlying the first portion (482) of the emitter (48), a peripheral portion (464) having a second base width (4643) larger than the first base width (4623) partly underlying the second portion (484) of the emitter (48), and a transition zone (466) of a third base width (4644) and lateral extent (4661) lying laterally between the first (462) and second (464) portions of the base (46), and a collector (44) underlying the base (46). The gain of the transistor (40, 40?) is much larger than a conventional bipolar transistor (20) made using the same CMOS process.

Abstract: An electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, comprises, first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first width and second width. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtl and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vtl, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

Abstract: Semiconductor devices (61) and methods (80-89, 100) are provided with dual passivation layers (56, 59). A semiconductor layer (34) is formed on a substrate (32) and covered by a first passivation layer (PL-1) (56). PL-1 (56) and part (341) of the semiconductor layer (34) are etched to form a device mesa (35). A second passivation layer (PL-2) (59) is formed over PL-1 (56) and exposed edges (44) of the mesa (35). Vias (90, 92, 93) are etched through PL-1 (56) and PL-2 (59) to the semiconductor layer (34) where source (40), drain (42) and gate are to be formed. Conductors (41, 43, 39) are applied in the vias (90, 92, 93) for ohmic contacts for the source-drain (40, 42) and a Schottky contact (39) for the gate. Interconnections (45, 47) over the edges (44) of the mesa (35) couple other circuit elements. PL-1 (56) avoids adverse surface states (52) near the gate and PL-2 (59) insulates edges (44) of the mesa (35) from overlying interconnections (45, 47) to avoid leakage currents (46).

Abstract: A foam-in-place apparatus includes a foam containment unit, a foam precursor storage unit, and a foam precursor heating unit, in one embodiment. During operation, the foam precursor heating unit is activated to provide activation heat to one or more foam precursor components stored within the foam precursor storage unit. The activation heat may cause temperatures of one or more of the foam precursor components to increase to temperatures within an activation temperature range. The pre-heated component or components are combined to produce an expansive foam, which is deployed in the foam containment unit, and which causes the foam containment unit to expand and displace or contour around any physical objects within the expansion limits of the foam containment unit.