Patents Represented by Attorney Shjerven, Morrill, MacPherson, Franklin & Friel LLP
  • Patent number: 5995994
    Abstract: The expression A-sign(A), where A is a signed binary integer represented in 2's complement form, sign(A) is equal to one when A is greater than zero, sign(A) is equal to zero when A is zero, and sign(A) is equal to negative one when A is less than zero, is calculated by bit-complementing A, bit-complementing (A-1) when A is less than zero, bit-complementing A when A is equal to zero, and bit-complementing (A+1) when A is greater than zero. Zero detect for A is provided by determining whether a first carry-out bit from (A+0) and a second carry-out bit from (A+1) have different logical values. In this manner, A-sign(A) can be calculated by a general purpose computer in a single instruction cycle.
    Type: Grant
    Filed: December 31, 1998
    Date of Patent: November 30, 1999
    Assignee: Samsung Semiconductor, Inc.
    Inventor: Roney S. Wong
  • Patent number: 5970020
    Abstract: A circuit is provided for controlling the set up of a memory address. The circuit includes a first latch circuit for latching a first memory address in response to a first simultaneous occurrence of a predetermined value for an output enable signal and a predetermined value for a row address strobe signal. A second latch circuit is coupled to the first latch circuit. The second latch circuit receives the first memory address from the first latch circuit and latches the first row address thereafter for decoding. The first latch circuit can latch a second memory address in response to a second simultaneous occurrence of the predetermined value for the output enable signal and the predetermined value for the row address strobe signal, the second simultaneous occurrence occurring while the first row address is being decoded.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: October 19, 1999
    Assignee: G-Link Technology
    Inventor: Adrian E. Ong
  • Patent number: 5923208
    Abstract: A temperature-to-voltage converter includes a first circuit for developing a signal having a positive temperature coefficient and a second circuit for developing a signal having a voltage offset and a negative temperature coefficient. The converter also includes an adder circuit configured to subtract the negative-temperature-coefficient signal from the positive-temperature-coefficient signal. The resulting difference signal is a low voltage that exhibits linear temperature-to-voltage conversion, allowing the converter to be powered by a low operating voltage.
    Type: Grant
    Filed: September 12, 1996
    Date of Patent: July 13, 1999
    Assignee: Telecom Semiconductor, Inc.
    Inventors: Ali Tasdighi, Chuong Nguyen