Abstract: A swing structure for a ceiling fan includes a reduction motor disposed with a driving wheel having its center fixed with a connecting rod. An intermediate aluminum ring is mounted on the outer circumference of the weight center of a fan motor, having a swing spindle provided with at least one first bearing, and a threading spindle disposed at the other end set therein with a second bearing. The swing spindle has one end connected with the connecting rod. The swing velocity of the ceiling fan is controlled by the reduction motor not affected by different rotating velocities of the fan motor. A hanging tube has its lower ends respectively fixed with the swing spindle and the threading spindle and its upper end secured on a support base, enabling a ceiling fan in stalled at different angles and still able to swing smoothly.

Abstract: A tubular connection structure having a tubular connection body, having a tubular space, each of the two sides of which has an open slot extended to form a pivotal base, the bottom of the tubular connection body extended to form a fastening base; a clasp lever pivotally connected to the pivotal bases, one end being a pressing portion, the other end being a stirring portion having a stirring lever accommodating base; a stirring lever accommodated in the stirring lever accommodating base, the top of the stirring lever being a stop convex portion configured to fasten the fastening base; a reset component one end of the reset component urged towards the stirring lever, the other end being urged towards the clasp lever; and at least two fixing members, connected to the clasp lever and the pivotal bases and connected to the stirring lever and the stirring lever accommodating base.

Abstract: A latched connector assembly includes a first connecting device and a second connecting device latched to each other. The first connecting device has a first casing and two terminal connectors received in the first casing. The first casing has first and second side walls. The first side walls have first engaging structures protruding outward. The second side walls each have an extending arm that has a second engaging structure. The second connecting device has a second casing and at least two terminal connectors received in the second casing. The second casing has third and fourth side walls. The third side walls have first engaging structures protruding outward. The fourth side walls each have a locking portion protruding outward for receiving the second engaging structures of the first connecting device. The terminal connectors are received, in opposite directions, in the first casing and the second casing, respectively.

Abstract: A self-calibration circuit of a nonvolatile memory includes a trimming data storage module, a sense amplifier module, a logic judgment module, and a scanning module. The nonvolatile memory circuit includes a memory cell array and the self-calibration circuit of the reading circuit of the nonvolatile memory. Without requiring an additional fuse or differential unit, the self-calibration circuit of a nonvolatile memory solves a deadlock problem securely and reliably without increasing circuit area and test cost, and be widely applied to OTP, MTP and EEPROM of various processes or various nonvolatile memories such as Flash EEPROM, MRAM, and FeRAM.

Abstract: A semiconductor-type electric connector against surge and static electricity includes a circuit board in the electric connector. The circuit board is provided with conductive terminals for external connection. The circuit board includes at least one electronic component which is a semiconductor chip. The electronic component is electrically connected to the conductive terminals of the circuit board in a parallel connection. The electronic component is conducted in a specific state, so that the electric connector is capable of being against surge and static electricity and convenient for maintenance.

Abstract: A sense amplifier and method of implementing includes a reference current generation circuit, which is used for providing a reference current with a settable temperature coefficient for a main circuit of the sense amplifier; the main circuit is used for comparing the reference current with a storage cell current, and distinguishing between 0 and 1 Storage Cell. A method of implementing the sense amplifier that is as below: With an additional current reference circuit, generating and inputting the reference current with a positive/negative/zero temperature coefficient into the main circuit, by mixing a proportional absolute temperature current and a constant current according to different ratios; a storage cell selection tube in a mirror branch of a biased current of the main circuit, so as to constitute a source degeneration circuit, making the biased current change with the power supply voltage and realizing a gain compensation function.

Abstract: Provided is a terminal pressing mold assembly including a first mold and a second mold having a projection. The first mold includes a main body, a pair of claws, and a groove. The main body includes a pair of first connecting portions. The claws each include a second connecting portion for adjoining a corresponding one of the first connecting portions, and adjoin the main body to thereby form the groove and a first slit between the claws. A second slit is formed between the main body and each of the claws. The claws include a pair of first guiding edges spaced apart by a first width. The projection includes a pair of second guiding edges spaced apart by a second width. The second width is not greater than the first width. The difference between the first and second widths is not greater than the width of the first slit.

Abstract: A method for verifying the bandwidth and phase of a digital power control system according to the present invention includes steps of: A. Disturbance Order Reading in which an A/D conversion unit receives an analog signal order and mix it with existing command components in a digital system unit; B. Phase Delay Compensation in which a phase lead compensator is designed that is based on the different sampling frequencies and time delay parameters of the digital system unit, and the phase lead compensator is added to the digital system unit; and C. System Measuring in which a mixed wave calculation unit and a supply unit are added to the digital system unit to make the analog command signal pass through the digital system unit and the mixed wave calculation unit to the supply unit and to further drive a power circuit.

Abstract: The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.

Abstract: The present invention discloses a configurable hierarchical comma-free Reed-Solomon decoding circuit and a method thereof. The design is based on an original hierarchical parallel architecture which not only completes a decoding process faster than conventional decoder, but also utilizes less hardware to perform various algorithms with less power consumed. The architecture of the present invention has higher decoding rate than the conventional systolic architecture by a cycle ratio of 22 to 94. Further, the present invention does not require the use of ROM to store 64 sets of codewords and uses logic gates less than one fourth of the logic gates than conventional systolic architecture. As a result, the circuit of the present invention occupies less area than the conventional architecture. The circuit of the present invention is also configurable for different applications, so it can always find an optimal compromise between speed and power consumption for various decoding requirements.