Abstract: A memory system having a main memory which is coupled to a plurality of parallel virtual access channels. Each of the virtual access channels provides a set of memory access resources for controlling the main memory. These memory access resources include cache resources (including cache chaining), burst mode operation control and precharge operation control. A plurality of the virtual access channels are cacheable virtual access channels, each of which includes a channel row cache memory for storing one or more cache entries and a channel row address register for storing corresponding cache address entries. One or more non-cacheable virtual access channels are provided by a bus bypass circuit. Each virtual access channel is addressable, such that particular memory masters can be assigned to access particular virtual access channels.

Abstract: A row decoder for controlling a plurality of selectable word-lines has one control line per block of N word-lines, K select lines, at least one disable line and one word-line driver per word-line. Each control line is activatable during a charge period and during an initial portion of a discharge period. Each select line is selectably high during the charge period. The disable line is active during the discharge period. Each driver includes an access transistor and a discharge transistor. The access transistor is located at one end of its word-line and the discharge transistor is connected at the other end. The access transistor is controlled by one control line and is connected between one select line and the word-line. The discharge transistor is controlled by one disable signal and is connected between the word-line and a ground supply.

Abstract: A new design methodology which utilizes a module-based architecture is used to implement customized VLSI designs. In accordance with this invention, the module-based architecture comprises a number of Matrix Transistor Logic (MTL) modules. Each MTL module has a control input buffer section, an output stage section, and a matrix array section. The matrix array section implements logic functions using Pass Transistor Logic technology. Three variables, each of which place a different constraint on the MTL modules, are used in an automated design procedure to implement the MTL modules.

Abstract: A conditioner assembly and a conditioner back support for conditioning a polishing pad of a chemical mechanical polishing device. The conditioner assembly comprises a conditioning head having a gimbal assembly, a shaft engaged to the conditioning head, and a linear torque bearing assembly slidably receiving the shaft. The linear torque bearing assembly is configured to operatively rotate the shaft assembly contemporaneously with allowing the shaft to extend and retract from a first open end of the linear torque bearing assembly. The conditioner assembly additionally comprises a bellows secured over the first open end and engaged to the conditioning head and a bearing housing disposed over a second open end of the linear torque bearing assembly. The bearing housing rotatably supports the linear torque bearing assembly such that a motor assembly can operatively drive the linear torque bearing assembly, the shaft, and the conditioning head.

Abstract: A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes three levels, a global switch matrix, a segment switch matrix and a block switch matrix. The block switch matrix provides a high speed signal path for signals within a programmable logic block. The segment switch matrix provides a high speed means of communication for signals within a segment, while the global switch matrix provides a high speed path for communication between segments. The hierarchical switch matrix of this invention provides a fixed, path independent, uniform, predictable and deterministic time delay for each group of signals routed through the hierarchical switch matrix.

Abstract: An even plurality of piezoelectric motor units operating directly on an element to be vertically translated, such as a car window, is disclosed. Each pair of piezoelectric motor units are located along an horizontal line on opposing sides of the element. The piezoelectric motors are preferably, asynchronously operated. An activation system for providing alternating current (AC) voltage to each of the piezoelectric motor units and converting direct current voltage to a sinusoidal square wave, is also included.